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torvaldstorvalds
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Merge tag 'for-linus-20121009' of git://git.infradead.org/mtd-2.6
Pull MTD updates from David Woodhouse: - Disable broken mtdchar mmap() on MMU systems - Additional ECC tests for NAND flash, and some test cleanups - New NAND and SPI chip support - Fixes/cleanup for SH FLCTL NAND controller driver - Improved hardware support for GPMI NAND controller - Conversions to device-tree support for various drivers - Removal of obsolete drivers (sbc8xxx, bcmring, etc.) - New LPC32xx drivers for MLC and SLC NAND - Further cleanup of NAND OOB/ECC handling - UAPI cleanup merge from David Howells (just moving files, since MTD headers were sorted out long ago to separate user-visible from kernel bits) * tag 'for-linus-20121009' of git://git.infradead.org/mtd-2.6: (168 commits) mtd: Disable mtdchar mmap on MMU systems UAPI: (Scripted) Disintegrate include/mtd mtd: nand: detect Samsung K9GBG08U0A, K9GAG08U0F ID mtd: nand: decode Hynix MLC, 6-byte ID length mtd: nand: increase max OOB size to 640 mtd: nand: add generic READ ID length calculation functions mtd: nand: split simple ID decode into its own function mtd: nand: split extended ID decoding into its own function mtd: nand: split BB marker options decoding into its own function mtd: nand: remove redundant ID read mtd: nand: remove unnecessary variable mtd: docg4: add missing HAS_IOMEM dependency mtd: gpmi: initialize the timing registers only one time mtd: gpmi: add EDO feature for imx6q mtd: gpmi: do not set the default values for the extra clocks mtd: gpmi: simplify the DLL setting code mtd: gpmi: add a new field for HW_GPMI_CTRL1 mtd: gpmi: do not get the clock frequency in gpmi_begin() mtd: gpmi: add a new field for HW_GPMI_TIMING1 mtd: add helpers to get the supportted ONFI timing mode ...
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‎Documentation/DocBook/mtdnand.tmpl

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1216,8 +1216,6 @@ in this page</entry>
12161216
#define NAND_BBT_LASTBLOCK 0x00000010
12171217
/* The bbt is at the given page, else we must scan for the bbt */
12181218
#define NAND_BBT_ABSPAGE 0x00000020
1219-
/* The bbt is at the given page, else we must scan for the bbt */
1220-
#define NAND_BBT_SEARCH 0x00000040
12211219
/* bbt is stored per chip on multichip devices */
12221220
#define NAND_BBT_PERCHIP 0x00000080
12231221
/* bbt has a version counter at offset veroffs */

‎Documentation/devicetree/bindings/arm/davinci/nand.txt

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,51 @@
1+
* Texas Instruments Davinci NAND
2+
3+
This file provides information, what the device node for the
4+
davinci nand interface contain.
5+
6+
Required properties:
7+
- compatible: "ti,davinci-nand";
8+
- reg : contain 2 offset/length values:
9+
- offset and length for the access window
10+
- offset and length for accessing the aemif control registers
11+
- ti,davinci-chipselect: Indicates on the davinci_nand driver which
12+
chipselect is used for accessing the nand.
13+
14+
Recommended properties :
15+
- ti,davinci-mask-ale: mask for ale
16+
- ti,davinci-mask-cle: mask for cle
17+
- ti,davinci-mask-chipsel: mask for chipselect
18+
- ti,davinci-ecc-mode: ECC mode valid values for davinci driver:
19+
- "none"
20+
- "soft"
21+
- "hw"
22+
- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
23+
- ti,davinci-nand-buswidth: buswidth 8 or 16
24+
- ti,davinci-nand-use-bbt: use flash based bad block table support.
25+
26+
Example (enbw_cmc board):
27+
aemif@60000000 {
28+
compatible = "ti,davinci-aemif";
29+
#address-cells = <2>;
30+
#size-cells = <1>;
31+
reg = <0x68000000 0x80000>;
32+
ranges = <2 0 0x60000000 0x02000000
33+
3 0 0x62000000 0x02000000
34+
4 0 0x64000000 0x02000000
35+
5 0 0x66000000 0x02000000
36+
6 0 0x68000000 0x02000000>;
37+
nand@3,0 {
38+
compatible = "ti,davinci-nand";
39+
reg = <3 0x0 0x807ff
40+
6 0x0 0x8000>;
41+
#address-cells = <1>;
42+
#size-cells = <1>;
43+
ti,davinci-chipselect = <1>;
44+
ti,davinci-mask-ale = <0>;
45+
ti,davinci-mask-cle = <0>;
46+
ti,davinci-mask-chipsel = <0>;
47+
ti,davinci-ecc-mode = "hw";
48+
ti,davinci-ecc-bits = <4>;
49+
ti,davinci-nand-use-bbt;
50+
};
51+
};

‎Documentation/devicetree/bindings/mtd/atmel-nand.txt

Lines changed: 39 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,9 @@ Atmel NAND flash
33
Required properties:
44
- compatible : "atmel,at91rm9200-nand".
55
- reg : should specify localbus address and size used for the chip,
6-
and if availlable the ECC.
6+
and hardware ECC controller if available.
7+
If the hardware ECC is PMECC, it should contain address and size for
8+
PMECC, PMECC Error Location controller and ROM which has lookup tables.
79
- atmel,nand-addr-offset : offset for the address latch.
810
- atmel,nand-cmd-offset : offset for the command latch.
911
- #address-cells, #size-cells : Must be present if the device has sub-nodes
@@ -16,6 +18,15 @@ Optional properties:
1618
- nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
1719
Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
1820
"soft_bch".
21+
- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware.
22+
Only supported by at91sam9x5 or later sam9 product.
23+
- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
24+
Controller. Supported values are: 2, 4, 8, 12, 24.
25+
- atmel,pmecc-sector-size : sector size for ECC computation. Supported values
26+
are: 512, 1024.
27+
- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
28+
for different sector size. First one is for sector size 512, the next is for
29+
sector size 1024.
1930
- nand-bus-width : 8 or 16 bus width if not present 8
2031
- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
2132

@@ -39,3 +50,30 @@ nand0: nand@40000000,0 {
3950
...
4051
};
4152
};
53+
54+
/* for PMECC supported chips */
55+
nand0: nand@40000000 {
56+
compatible = "atmel,at91rm9200-nand";
57+
#address-cells = <1>;
58+
#size-cells = <1>;
59+
reg = < 0x40000000 0x10000000 /* bus addr & size */
60+
0xffffe000 0x00000600 /* PMECC addr & size */
61+
0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */
62+
0x00100000 0x00100000 /* ROM addr & size */
63+
>;
64+
atmel,nand-addr-offset = <21>; /* ale */
65+
atmel,nand-cmd-offset = <22>; /* cle */
66+
nand-on-flash-bbt;
67+
nand-ecc-mode = "hw";
68+
atmel,has-pmecc; /* enable PMECC */
69+
atmel,pmecc-cap = <2>;
70+
atmel,pmecc-sector-size = <512>;
71+
atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
72+
gpios = <&pioD 5 0 /* rdy */
73+
&pioD 4 0 /* nce */
74+
0 /* cd */
75+
>;
76+
partition@0 {
77+
...
78+
};
79+
};

‎Documentation/devicetree/bindings/mtd/gpmi-nand.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,10 @@ Required properties:
1212
- interrupt-names : The interrupt names "gpmi-dma", "bch";
1313
- fsl,gpmi-dma-channel : Should contain the dma channel it uses.
1414

15+
Optional properties:
16+
- nand-on-flash-bbt: boolean to enable on flash bbt option if not
17+
present false
18+
1519
The device tree may optionally contain sub-nodes describing partitions of the
1620
address space. See partition.txt for more detail.
1721

‎Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,50 @@
1+
NXP LPC32xx SoC NAND MLC controller
2+
3+
Required properties:
4+
- compatible: "nxp,lpc3220-mlc"
5+
- reg: Address and size of the controller
6+
- interrupts: The NAND interrupt specification
7+
- gpios: GPIO specification for NAND write protect
8+
9+
The following required properties are very controller specific. See the LPC32xx
10+
User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
11+
Hz, to make them independent of actual clock speed and to provide for good
12+
accuracy:)
13+
- nxp,tcea_delay: TCEA_DELAY
14+
- nxp,busy_delay: BUSY_DELAY
15+
- nxp,nand_ta: NAND_TA
16+
- nxp,rd_high: RD_HIGH
17+
- nxp,rd_low: RD_LOW
18+
- nxp,wr_high: WR_HIGH
19+
- nxp,wr_low: WR_LOW
20+
21+
Optional subnodes:
22+
- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
23+
24+
Example:
25+
26+
mlc: flash@200A8000 {
27+
compatible = "nxp,lpc3220-mlc";
28+
reg = <0x200A8000 0x11000>;
29+
interrupts = <11 0>;
30+
#address-cells = <1>;
31+
#size-cells = <1>;
32+
33+
nxp,tcea-delay = <333333333>;
34+
nxp,busy-delay = <10000000>;
35+
nxp,nand-ta = <18181818>;
36+
nxp,rd-high = <31250000>;
37+
nxp,rd-low = <45454545>;
38+
nxp,wr-high = <40000000>;
39+
nxp,wr-low = <83333333>;
40+
gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
41+
42+
mtd0@00000000 {
43+
label = "boot";
44+
reg = <0x00000000 0x00064000>;
45+
read-only;
46+
};
47+
48+
...
49+
50+
};

‎Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
1+
NXP LPC32xx SoC NAND SLC controller
2+
3+
Required properties:
4+
- compatible: "nxp,lpc3220-slc"
5+
- reg: Address and size of the controller
6+
- nand-on-flash-bbt: Use bad block table on flash
7+
- gpios: GPIO specification for NAND write protect
8+
9+
The following required properties are very controller specific. See the LPC32xx
10+
User Manual:
11+
- nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
12+
- nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
13+
(The following values are specified in Hz, to make them independent of actual
14+
clock speed:)
15+
- nxp,wwidth: Write pulse width (W_WIDTH)
16+
- nxp,whold: Write hold time (W_HOLD)
17+
- nxp,wsetup: Write setup time (W_SETUP)
18+
- nxp,rwidth: Read pulse width (R_WIDTH)
19+
- nxp,rhold: Read hold time (R_HOLD)
20+
- nxp,rsetup: Read setup time (R_SETUP)
21+
22+
Optional subnodes:
23+
- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
24+
25+
Example:
26+
27+
slc: flash@20020000 {
28+
compatible = "nxp,lpc3220-slc";
29+
reg = <0x20020000 0x1000>;
30+
#address-cells = <1>;
31+
#size-cells = <1>;
32+
33+
nxp,wdr-clks = <14>;
34+
nxp,wwidth = <40000000>;
35+
nxp,whold = <100000000>;
36+
nxp,wsetup = <100000000>;
37+
nxp,rdr-clks = <14>;
38+
nxp,rwidth = <40000000>;
39+
nxp,rhold = <66666666>;
40+
nxp,rsetup = <100000000>;
41+
nand-on-flash-bbt;
42+
gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
43+
44+
mtd0@00000000 {
45+
label = "phy3250-boot";
46+
reg = <0x00000000 0x00064000>;
47+
read-only;
48+
};
49+
50+
...
51+
52+
};

‎Documentation/devicetree/bindings/mtd/mtd-physmap.txt

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,13 @@ file systems on embedded devices.
1616
- #address-cells, #size-cells : Must be present if the device has
1717
sub-nodes representing partitions (see below). In this case
1818
both #address-cells and #size-cells must be equal to 1.
19+
- no-unaligned-direct-access: boolean to disable the default direct
20+
mapping of the flash.
21+
On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause
22+
problems with JFFS2 usage, as the local bus (LPB) doesn't support
23+
unaligned accesses as implemented in the JFFS2 code via memcpy().
24+
By defining "no-unaligned-direct-access", the flash will not be
25+
exposed directly to the MTD users (e.g. JFFS2) any more.
1926

2027
For JEDEC compatible devices, the following additional properties
2128
are defined:

‎arch/arm/boot/dts/imx51.dtsi

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -407,6 +407,13 @@
407407
status = "disabled";
408408
};
409409

410+
nand@83fdb000 {
411+
compatible = "fsl,imx51-nand";
412+
reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
413+
interrupts = <8>;
414+
status = "disabled";
415+
};
416+
410417
ssi3: ssi@83fe8000 {
411418
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
412419
reg = <0x83fe8000 0x4000>;

‎arch/arm/boot/dts/imx53.dtsi

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -518,6 +518,13 @@
518518
status = "disabled";
519519
};
520520

521+
nand@63fdb000 {
522+
compatible = "fsl,imx53-nand";
523+
reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
524+
interrupts = <8>;
525+
status = "disabled";
526+
};
527+
521528
ssi3: ssi@63fe8000 {
522529
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
523530
reg = <0x63fe8000 0x4000>;

‎arch/arm/configs/cam60_defconfig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,6 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
4949
CONFIG_MTD_PLATRAM=m
5050
CONFIG_MTD_DATAFLASH=y
5151
CONFIG_MTD_NAND=y
52-
CONFIG_MTD_NAND_VERIFY_WRITE=y
5352
CONFIG_MTD_NAND_ATMEL=y
5453
CONFIG_BLK_DEV_LOOP=y
5554
CONFIG_BLK_DEV_RAM=y

‎arch/arm/configs/corgi_defconfig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,6 @@ CONFIG_MTD_BLOCK=y
9797
CONFIG_MTD_ROM=y
9898
CONFIG_MTD_COMPLEX_MAPPINGS=y
9999
CONFIG_MTD_NAND=y
100-
CONFIG_MTD_NAND_VERIFY_WRITE=y
101100
CONFIG_MTD_NAND_SHARPSL=y
102101
CONFIG_BLK_DEV_LOOP=y
103102
CONFIG_IDE=y

‎arch/arm/configs/ep93xx_defconfig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,6 @@ CONFIG_MTD_CFI_STAA=y
6161
CONFIG_MTD_ROM=y
6262
CONFIG_MTD_PHYSMAP=y
6363
CONFIG_MTD_NAND=y
64-
CONFIG_MTD_NAND_VERIFY_WRITE=y
6564
CONFIG_BLK_DEV_NBD=y
6665
CONFIG_EEPROM_LEGACY=y
6766
CONFIG_SCSI=y

‎arch/arm/configs/mini2440_defconfig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -102,7 +102,6 @@ CONFIG_MTD_CFI_STAA=y
102102
CONFIG_MTD_RAM=y
103103
CONFIG_MTD_ROM=y
104104
CONFIG_MTD_NAND=y
105-
CONFIG_MTD_NAND_VERIFY_WRITE=y
106105
CONFIG_MTD_NAND_S3C2410=y
107106
CONFIG_MTD_NAND_PLATFORM=y
108107
CONFIG_MTD_LPDDR=y

‎arch/arm/configs/mv78xx0_defconfig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,6 @@ CONFIG_MTD_CFI_INTELEXT=y
4949
CONFIG_MTD_CFI_AMDSTD=y
5050
CONFIG_MTD_PHYSMAP=y
5151
CONFIG_MTD_NAND=y
52-
CONFIG_MTD_NAND_VERIFY_WRITE=y
5352
CONFIG_MTD_NAND_ORION=y
5453
CONFIG_BLK_DEV_LOOP=y
5554
# CONFIG_SCSI_PROC_FS is not set

‎arch/arm/configs/nhk8815_defconfig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,6 @@ CONFIG_MTD_CHAR=y
5757
CONFIG_MTD_BLOCK=y
5858
CONFIG_MTD_NAND=y
5959
CONFIG_MTD_NAND_ECC_SMC=y
60-
CONFIG_MTD_NAND_VERIFY_WRITE=y
6160
CONFIG_MTD_NAND_NOMADIK=y
6261
CONFIG_MTD_ONENAND=y
6362
CONFIG_MTD_ONENAND_VERIFY_WRITE=y

‎arch/arm/configs/orion5x_defconfig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,6 @@ CONFIG_MTD_CFI_INTELEXT=y
7272
CONFIG_MTD_CFI_AMDSTD=y
7373
CONFIG_MTD_PHYSMAP=y
7474
CONFIG_MTD_NAND=y
75-
CONFIG_MTD_NAND_VERIFY_WRITE=y
7675
CONFIG_MTD_NAND_PLATFORM=y
7776
CONFIG_MTD_NAND_ORION=y
7877
CONFIG_BLK_DEV_LOOP=y

‎arch/arm/configs/pxa3xx_defconfig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,6 @@ CONFIG_MTD_CONCAT=y
3636
CONFIG_MTD_CHAR=y
3737
CONFIG_MTD_BLOCK=y
3838
CONFIG_MTD_NAND=y
39-
CONFIG_MTD_NAND_VERIFY_WRITE=y
4039
CONFIG_MTD_NAND_PXA3xx=y
4140
CONFIG_MTD_NAND_PXA3xx_BUILTIN=y
4241
CONFIG_MTD_ONENAND=y

‎arch/arm/configs/spitz_defconfig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,6 @@ CONFIG_MTD_BLOCK=y
9494
CONFIG_MTD_ROM=y
9595
CONFIG_MTD_COMPLEX_MAPPINGS=y
9696
CONFIG_MTD_NAND=y
97-
CONFIG_MTD_NAND_VERIFY_WRITE=y
9897
CONFIG_MTD_NAND_SHARPSL=y
9998
CONFIG_BLK_DEV_LOOP=y
10099
CONFIG_IDE=y

‎arch/arm/mach-clps711x/autcpu12.c

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,8 @@
2323
#include <linux/string.h>
2424
#include <linux/mm.h>
2525
#include <linux/io.h>
26+
#include <linux/ioport.h>
27+
#include <linux/platform_device.h>
2628

2729
#include <mach/hardware.h>
2830
#include <asm/sizes.h>
@@ -62,9 +64,26 @@ void __init autcpu12_map_io(void)
6264
iotable_init(autcpu12_io_desc, ARRAY_SIZE(autcpu12_io_desc));
6365
}
6466

67+
static struct resource autcpu12_nvram_resource[] __initdata = {
68+
DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"),
69+
};
70+
71+
static struct platform_device autcpu12_nvram_pdev __initdata = {
72+
.name = "autcpu12_nvram",
73+
.id = -1,
74+
.resource = autcpu12_nvram_resource,
75+
.num_resources = ARRAY_SIZE(autcpu12_nvram_resource),
76+
};
77+
78+
static void __init autcpu12_init(void)
79+
{
80+
platform_device_register(&autcpu12_nvram_pdev);
81+
}
82+
6583
MACHINE_START(AUTCPU12, "autronix autcpu12")
6684
/* Maintainer: Thomas Gleixner */
6785
.atag_offset = 0x20000,
86+
.init_machine = autcpu12_init,
6887
.map_io = autcpu12_map_io,
6988
.init_irq = clps711x_init_irq,
7089
.timer = &clps711x_timer,

‎arch/arm/mach-imx/clk-imx51-imx53.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -369,6 +369,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
369369
clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
370370
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
371371
clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
372+
clk_register_clkdev(clk[nfc_gate], NULL, "83fdb000.nand");
372373

373374
/* set the usboh3 parent to pll2_sw */
374375
clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
@@ -461,6 +462,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
461462
clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
462463
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
463464
clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
465+
clk_register_clkdev(clk[nfc_gate], NULL, "63fdb000.nand");
464466
clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can");
465467
clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
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clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");

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