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Rob Herringolofj
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ARM: dts: fix highbank cpu mpidr values
With the addition of commit a0ae024 (ARM: kernel: add device tree init map function), the cpu reg values must match the cpu mpidr register or we'll get warnings. For some reason, the CLUSTERID on highbank is 9, so the reg value needs to be 0x90n to quiet the warnings. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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arch/arm/boot/dts/highbank.dts

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -30,37 +30,37 @@
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#address-cells = <1>;
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#size-cells = <0>;
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33-
cpu@0 {
33+
cpu@900 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
36-
reg = <0>;
36+
reg = <0x900>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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42-
cpu@1 {
42+
cpu@901 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
45-
reg = <1>;
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reg = <0x901>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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51-
cpu@2 {
51+
cpu@902 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
54-
reg = <2>;
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reg = <0x902>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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60-
cpu@3 {
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cpu@903 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
63-
reg = <3>;
63+
reg = <0x903>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";

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