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torvaldstorvalds
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Pull networking fixes from David Miller: 1) Revert iwlwifi reclaimed packet tracking, it causes problems for a bunch of folks. From Emmanuel Grumbach. 2) Work limiting code in brcmsmac wifi driver can clear tx status without processing the event. From Arend van Spriel. 3) rtlwifi USB driver processes wrong SKB, fix from Larry Finger. 4) l2tp tunnel delete can race with close, fix from Tom Parkin. 5) pktgen_add_device() failures are not checked at all, fix from Cong Wang. 6) Fix unintentional removal of carrier off from tun_detach(), otherwise we confuse userspace, from Michael S. Tsirkin. 7) Don't leak socket reference counts and ubufs in vhost-net driver, from Jason Wang. 8) vmxnet3 driver gets it's initial carrier state wrong, fix from Neil Horman. 9) Protect against USB networking devices which spam the host with 0 length frames, from Bjørn Mork. 10) Prevent neighbour overflows in ipv6 for locally destined routes, from Marcelo Ricardo. This is the best short-term fix for this, a longer term fix has been implemented in net-next. 11) L2TP uses ipv4 datagram routines in it's ipv6 code, whoops. This mistake is largely because the ipv6 functions don't even have some kind of prefix in their names to suggest they are ipv6 specific. From Tom Parkin. 12) Check SYN packet drops properly in tcp_rcv_fastopen_synack(), from Yuchung Cheng. 13) Fix races and TX skb freeing bugs in via-rhine's NAPI support, from Francois Romieu and your's truly. 14) Fix infinite loops and divides by zero in TCP congestion window handling, from Eric Dumazet, Neal Cardwell, and Ilpo Järvinen. 15) AF_PACKET tx ring handling can leak kernel memory to userspace, fix from Phil Sutter. 16) Fix error handling in ipv6 GRE tunnel transmit, from Tommi Rantala. 17) Protect XEN netback driver against hostile frontend putting garbage into the rings, don't leak pages in TX GOP checking, and add proper resource releasing in error path of xen_netbk_get_requests(). From Ian Campbell. 18) SCTP authentication keys should be cleared out and released with kzfree(), from Daniel Borkmann. 19) L2TP is a bit too clever trying to maintain skb->truesize, and ends up corrupting socket memory accounting to the point where packet sending is halted indefinitely. Just remove the adjustments entirely, they aren't really needed. From Eric Dumazet. 20) ATM Iphase driver uses a data type with the same name as the S390 headers, rename to fix the build. From Heiko Carstens. 21) Fix a typo in copying the inner network header offset from one SKB to another, from Pravin B Shelar. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (56 commits) net: sctp: sctp_endpoint_free: zero out secret key data net: sctp: sctp_setsockopt_auth_key: use kzfree instead of kfree atm/iphase: rename fregt_t -> ffreg_t net: usb: fix regression from FLAG_NOARP code l2tp: dont play with skb->truesize net: sctp: sctp_auth_key_put: use kzfree instead of kfree netback: correct netbk_tx_err to handle wrap around. xen/netback: free already allocated memory on failure in xen_netbk_get_requests xen/netback: don't leak pages on failure in xen_netbk_tx_check_gop. xen/netback: shutdown the ring if it contains garbage. net: qmi_wwan: add more Huawei devices, including E320 net: cdc_ncm: add another Huawei vendor specific device ipv6/ip6_gre: fix error case handling in ip6gre_tunnel_xmit() tcp: fix for zero packets_in_flight was too broad brcmsmac: rework of mac80211 .flush() callback operation ssb: unregister gpios before unloading ssb bcma: unregister gpios before unloading bcma rtlwifi: Fix scheduling while atomic bug net: usbnet: fix tx_dropped statistics tcp: ipv6: Update MIB counters for drops ...
2 parents 2a1a6e7 + a1c83b0 commit e06b840

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+649
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lines changed

‎drivers/atm/iphase.h

Lines changed: 73 additions & 73 deletions
Original file line numberDiff line numberDiff line change
@@ -636,82 +636,82 @@ struct rx_buf_desc {
636636
#define SEG_BASE IPHASE5575_FRAG_CONTROL_REG_BASE
637637
#define REASS_BASE IPHASE5575_REASS_CONTROL_REG_BASE
638638

639-
typedef volatile u_int freg_t;
639+
typedef volatile u_int ffreg_t;
640640
typedef u_int rreg_t;
641641

642642
typedef struct _ffredn_t {
643-
freg_t idlehead_high; /* Idle cell header (high) */
644-
freg_t idlehead_low; /* Idle cell header (low) */
645-
freg_t maxrate; /* Maximum rate */
646-
freg_t stparms; /* Traffic Management Parameters */
647-
freg_t abrubr_abr; /* ABRUBR Priority Byte 1, TCR Byte 0 */
648-
freg_t rm_type; /* */
649-
u_int filler5[0x17 - 0x06];
650-
freg_t cmd_reg; /* Command register */
651-
u_int filler18[0x20 - 0x18];
652-
freg_t cbr_base; /* CBR Pointer Base */
653-
freg_t vbr_base; /* VBR Pointer Base */
654-
freg_t abr_base; /* ABR Pointer Base */
655-
freg_t ubr_base; /* UBR Pointer Base */
656-
u_int filler24;
657-
freg_t vbrwq_base; /* VBR Wait Queue Base */
658-
freg_t abrwq_base; /* ABR Wait Queue Base */
659-
freg_t ubrwq_base; /* UBR Wait Queue Base */
660-
freg_t vct_base; /* Main VC Table Base */
661-
freg_t vcte_base; /* Extended Main VC Table Base */
662-
u_int filler2a[0x2C - 0x2A];
663-
freg_t cbr_tab_beg; /* CBR Table Begin */
664-
freg_t cbr_tab_end; /* CBR Table End */
665-
freg_t cbr_pointer; /* CBR Pointer */
666-
u_int filler2f[0x30 - 0x2F];
667-
freg_t prq_st_adr; /* Packet Ready Queue Start Address */
668-
freg_t prq_ed_adr; /* Packet Ready Queue End Address */
669-
freg_t prq_rd_ptr; /* Packet Ready Queue read pointer */
670-
freg_t prq_wr_ptr; /* Packet Ready Queue write pointer */
671-
freg_t tcq_st_adr; /* Transmit Complete Queue Start Address*/
672-
freg_t tcq_ed_adr; /* Transmit Complete Queue End Address */
673-
freg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */
674-
freg_t tcq_wr_ptr; /* Transmit Complete Queue write pointer*/
675-
u_int filler38[0x40 - 0x38];
676-
freg_t queue_base; /* Base address for PRQ and TCQ */
677-
freg_t desc_base; /* Base address of descriptor table */
678-
u_int filler42[0x45 - 0x42];
679-
freg_t mode_reg_0; /* Mode register 0 */
680-
freg_t mode_reg_1; /* Mode register 1 */
681-
freg_t intr_status_reg;/* Interrupt Status register */
682-
freg_t mask_reg; /* Mask Register */
683-
freg_t cell_ctr_high1; /* Total cell transfer count (high) */
684-
freg_t cell_ctr_lo1; /* Total cell transfer count (low) */
685-
freg_t state_reg; /* Status register */
686-
u_int filler4c[0x58 - 0x4c];
687-
freg_t curr_desc_num; /* Contains the current descriptor num */
688-
freg_t next_desc; /* Next descriptor */
689-
freg_t next_vc; /* Next VC */
690-
u_int filler5b[0x5d - 0x5b];
691-
freg_t present_slot_cnt;/* Present slot count */
692-
u_int filler5e[0x6a - 0x5e];
693-
freg_t new_desc_num; /* New descriptor number */
694-
freg_t new_vc; /* New VC */
695-
freg_t sched_tbl_ptr; /* Schedule table pointer */
696-
freg_t vbrwq_wptr; /* VBR wait queue write pointer */
697-
freg_t vbrwq_rptr; /* VBR wait queue read pointer */
698-
freg_t abrwq_wptr; /* ABR wait queue write pointer */
699-
freg_t abrwq_rptr; /* ABR wait queue read pointer */
700-
freg_t ubrwq_wptr; /* UBR wait queue write pointer */
701-
freg_t ubrwq_rptr; /* UBR wait queue read pointer */
702-
freg_t cbr_vc; /* CBR VC */
703-
freg_t vbr_sb_vc; /* VBR SB VC */
704-
freg_t abr_sb_vc; /* ABR SB VC */
705-
freg_t ubr_sb_vc; /* UBR SB VC */
706-
freg_t vbr_next_link; /* VBR next link */
707-
freg_t abr_next_link; /* ABR next link */
708-
freg_t ubr_next_link; /* UBR next link */
709-
u_int filler7a[0x7c-0x7a];
710-
freg_t out_rate_head; /* Out of rate head */
711-
u_int filler7d[0xca-0x7d]; /* pad out to full address space */
712-
freg_t cell_ctr_high1_nc;/* Total cell transfer count (high) */
713-
freg_t cell_ctr_lo1_nc;/* Total cell transfer count (low) */
714-
u_int fillercc[0x100-0xcc]; /* pad out to full address space */
643+
ffreg_t idlehead_high; /* Idle cell header (high) */
644+
ffreg_t idlehead_low; /* Idle cell header (low) */
645+
ffreg_t maxrate; /* Maximum rate */
646+
ffreg_t stparms; /* Traffic Management Parameters */
647+
ffreg_t abrubr_abr; /* ABRUBR Priority Byte 1, TCR Byte 0 */
648+
ffreg_t rm_type; /* */
649+
u_int filler5[0x17 - 0x06];
650+
ffreg_t cmd_reg; /* Command register */
651+
u_int filler18[0x20 - 0x18];
652+
ffreg_t cbr_base; /* CBR Pointer Base */
653+
ffreg_t vbr_base; /* VBR Pointer Base */
654+
ffreg_t abr_base; /* ABR Pointer Base */
655+
ffreg_t ubr_base; /* UBR Pointer Base */
656+
u_int filler24;
657+
ffreg_t vbrwq_base; /* VBR Wait Queue Base */
658+
ffreg_t abrwq_base; /* ABR Wait Queue Base */
659+
ffreg_t ubrwq_base; /* UBR Wait Queue Base */
660+
ffreg_t vct_base; /* Main VC Table Base */
661+
ffreg_t vcte_base; /* Extended Main VC Table Base */
662+
u_int filler2a[0x2C - 0x2A];
663+
ffreg_t cbr_tab_beg; /* CBR Table Begin */
664+
ffreg_t cbr_tab_end; /* CBR Table End */
665+
ffreg_t cbr_pointer; /* CBR Pointer */
666+
u_int filler2f[0x30 - 0x2F];
667+
ffreg_t prq_st_adr; /* Packet Ready Queue Start Address */
668+
ffreg_t prq_ed_adr; /* Packet Ready Queue End Address */
669+
ffreg_t prq_rd_ptr; /* Packet Ready Queue read pointer */
670+
ffreg_t prq_wr_ptr; /* Packet Ready Queue write pointer */
671+
ffreg_t tcq_st_adr; /* Transmit Complete Queue Start Address*/
672+
ffreg_t tcq_ed_adr; /* Transmit Complete Queue End Address */
673+
ffreg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */
674+
ffreg_t tcq_wr_ptr; /* Transmit Complete Queue write pointer*/
675+
u_int filler38[0x40 - 0x38];
676+
ffreg_t queue_base; /* Base address for PRQ and TCQ */
677+
ffreg_t desc_base; /* Base address of descriptor table */
678+
u_int filler42[0x45 - 0x42];
679+
ffreg_t mode_reg_0; /* Mode register 0 */
680+
ffreg_t mode_reg_1; /* Mode register 1 */
681+
ffreg_t intr_status_reg;/* Interrupt Status register */
682+
ffreg_t mask_reg; /* Mask Register */
683+
ffreg_t cell_ctr_high1; /* Total cell transfer count (high) */
684+
ffreg_t cell_ctr_lo1; /* Total cell transfer count (low) */
685+
ffreg_t state_reg; /* Status register */
686+
u_int filler4c[0x58 - 0x4c];
687+
ffreg_t curr_desc_num; /* Contains the current descriptor num */
688+
ffreg_t next_desc; /* Next descriptor */
689+
ffreg_t next_vc; /* Next VC */
690+
u_int filler5b[0x5d - 0x5b];
691+
ffreg_t present_slot_cnt;/* Present slot count */
692+
u_int filler5e[0x6a - 0x5e];
693+
ffreg_t new_desc_num; /* New descriptor number */
694+
ffreg_t new_vc; /* New VC */
695+
ffreg_t sched_tbl_ptr; /* Schedule table pointer */
696+
ffreg_t vbrwq_wptr; /* VBR wait queue write pointer */
697+
ffreg_t vbrwq_rptr; /* VBR wait queue read pointer */
698+
ffreg_t abrwq_wptr; /* ABR wait queue write pointer */
699+
ffreg_t abrwq_rptr; /* ABR wait queue read pointer */
700+
ffreg_t ubrwq_wptr; /* UBR wait queue write pointer */
701+
ffreg_t ubrwq_rptr; /* UBR wait queue read pointer */
702+
ffreg_t cbr_vc; /* CBR VC */
703+
ffreg_t vbr_sb_vc; /* VBR SB VC */
704+
ffreg_t abr_sb_vc; /* ABR SB VC */
705+
ffreg_t ubr_sb_vc; /* UBR SB VC */
706+
ffreg_t vbr_next_link; /* VBR next link */
707+
ffreg_t abr_next_link; /* ABR next link */
708+
ffreg_t ubr_next_link; /* UBR next link */
709+
u_int filler7a[0x7c-0x7a];
710+
ffreg_t out_rate_head; /* Out of rate head */
711+
u_int filler7d[0xca-0x7d]; /* pad out to full address space */
712+
ffreg_t cell_ctr_high1_nc;/* Total cell transfer count (high) */
713+
ffreg_t cell_ctr_lo1_nc;/* Total cell transfer count (low) */
714+
u_int fillercc[0x100-0xcc]; /* pad out to full address space */
715715
} ffredn_t;
716716

717717
typedef struct _rfredn_t {

‎drivers/bcma/bcma_private.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -94,11 +94,16 @@ void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
9494
#ifdef CONFIG_BCMA_DRIVER_GPIO
9595
/* driver_gpio.c */
9696
int bcma_gpio_init(struct bcma_drv_cc *cc);
97+
int bcma_gpio_unregister(struct bcma_drv_cc *cc);
9798
#else
9899
static inline int bcma_gpio_init(struct bcma_drv_cc *cc)
99100
{
100101
return -ENOTSUPP;
101102
}
103+
static inline int bcma_gpio_unregister(struct bcma_drv_cc *cc)
104+
{
105+
return 0;
106+
}
102107
#endif /* CONFIG_BCMA_DRIVER_GPIO */
103108

104109
#endif

‎drivers/bcma/driver_chipcommon_nflash.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ int bcma_nflash_init(struct bcma_drv_cc *cc)
2121
struct bcma_bus *bus = cc->core->bus;
2222

2323
if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
24-
cc->core->id.rev != 0x38) {
24+
cc->core->id.rev != 38) {
2525
bcma_err(bus, "NAND flash on unsupported board!\n");
2626
return -ENOTSUPP;
2727
}

‎drivers/bcma/driver_gpio.c

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -96,3 +96,8 @@ int bcma_gpio_init(struct bcma_drv_cc *cc)
9696

9797
return gpiochip_add(chip);
9898
}
99+
100+
int bcma_gpio_unregister(struct bcma_drv_cc *cc)
101+
{
102+
return gpiochip_remove(&cc->gpio);
103+
}

‎drivers/bcma/main.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -268,6 +268,13 @@ int bcma_bus_register(struct bcma_bus *bus)
268268
void bcma_bus_unregister(struct bcma_bus *bus)
269269
{
270270
struct bcma_device *cores[3];
271+
int err;
272+
273+
err = bcma_gpio_unregister(&bus->drv_cc);
274+
if (err == -EBUSY)
275+
bcma_err(bus, "Some GPIOs are still in use.\n");
276+
else if (err)
277+
bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
271278

272279
cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
273280
cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);

‎drivers/net/bonding/bond_sysfs.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1053,6 +1053,7 @@ static ssize_t bonding_store_primary(struct device *d,
10531053
pr_info("%s: Setting primary slave to None.\n",
10541054
bond->dev->name);
10551055
bond->primary_slave = NULL;
1056+
memset(bond->params.primary, 0, sizeof(bond->params.primary));
10561057
bond_select_active_slave(bond);
10571058
goto out;
10581059
}

‎drivers/net/can/c_can/c_can.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -488,8 +488,12 @@ static void c_can_setup_receive_object(struct net_device *dev, int iface,
488488

489489
priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface),
490490
IFX_WRITE_LOW_16BIT(mask));
491+
492+
/* According to C_CAN documentation, the reserved bit
493+
* in IFx_MASK2 register is fixed 1
494+
*/
491495
priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface),
492-
IFX_WRITE_HIGH_16BIT(mask));
496+
IFX_WRITE_HIGH_16BIT(mask) | BIT(13));
493497

494498
priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface),
495499
IFX_WRITE_LOW_16BIT(id));

‎drivers/net/ethernet/emulex/benet/be.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -36,13 +36,13 @@
3636

3737
#define DRV_VER "4.4.161.0u"
3838
#define DRV_NAME "be2net"
39-
#define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
40-
#define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
41-
#define OC_NAME "Emulex OneConnect 10Gbps NIC"
39+
#define BE_NAME "Emulex BladeEngine2"
40+
#define BE3_NAME "Emulex BladeEngine3"
41+
#define OC_NAME "Emulex OneConnect"
4242
#define OC_NAME_BE OC_NAME "(be3)"
4343
#define OC_NAME_LANCER OC_NAME "(Lancer)"
4444
#define OC_NAME_SH OC_NAME "(Skyhawk)"
45-
#define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver"
45+
#define DRV_DESC "Emulex OneConnect 10Gbps NIC Driver"
4646

4747
#define BE_VENDOR_ID 0x19a2
4848
#define EMULEX_VENDOR_ID 0x10df

‎drivers/net/ethernet/emulex/benet/be_main.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@
2525
MODULE_VERSION(DRV_VER);
2626
MODULE_DEVICE_TABLE(pci, be_dev_ids);
2727
MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
28-
MODULE_AUTHOR("ServerEngines Corporation");
28+
MODULE_AUTHOR("Emulex Corporation");
2929
MODULE_LICENSE("GPL");
3030

3131
static unsigned int num_vfs;

‎drivers/net/ethernet/intel/e1000e/defines.h

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -232,6 +232,7 @@
232232
#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
233233
#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
234234
#define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */
235+
#define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */
235236
#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
236237
#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
237238
#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
@@ -389,6 +390,12 @@
389390

390391
#define E1000_PBS_16K E1000_PBA_16K
391392

393+
/* Uncorrectable/correctable ECC Error counts and enable bits */
394+
#define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF
395+
#define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00
396+
#define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8
397+
#define E1000_PBECCSTS_ECC_ENABLE 0x00010000
398+
392399
#define IFS_MAX 80
393400
#define IFS_MIN 40
394401
#define IFS_RATIO 4
@@ -408,6 +415,7 @@
408415
#define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
409416
#define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
410417
#define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
418+
#define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */
411419
#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
412420
#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
413421
#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
@@ -443,6 +451,7 @@
443451
#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
444452
#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
445453
#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
454+
#define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */
446455
#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
447456
#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
448457
#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */

‎drivers/net/ethernet/intel/e1000e/e1000.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -309,6 +309,8 @@ struct e1000_adapter {
309309

310310
struct napi_struct napi;
311311

312+
unsigned int uncorr_errors; /* uncorrectable ECC errors */
313+
unsigned int corr_errors; /* correctable ECC errors */
312314
unsigned int restart_queue;
313315
u32 txd_cmd;
314316

‎drivers/net/ethernet/intel/e1000e/ethtool.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -108,6 +108,8 @@ static const struct e1000_stats e1000_gstrings_stats[] = {
108108
E1000_STAT("dropped_smbus", stats.mgpdc),
109109
E1000_STAT("rx_dma_failed", rx_dma_failed),
110110
E1000_STAT("tx_dma_failed", tx_dma_failed),
111+
E1000_STAT("uncorr_ecc_errors", uncorr_errors),
112+
E1000_STAT("corr_ecc_errors", corr_errors),
111113
};
112114

113115
#define E1000_GLOBAL_STATS_LEN ARRAY_SIZE(e1000_gstrings_stats)

‎drivers/net/ethernet/intel/e1000e/hw.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,7 @@ enum e1e_registers {
7777
#define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
7878
E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
7979
E1000_PBS = 0x01008, /* Packet Buffer Size */
80+
E1000_PBECCSTS = 0x0100C, /* Packet Buffer ECC Status - RW */
8081
E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
8182
E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
8283
E1000_FLOP = 0x0103C, /* FLASH Opcode Register */

‎drivers/net/ethernet/intel/e1000e/ich8lan.c

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3624,6 +3624,17 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
36243624
if (hw->mac.type == e1000_ich8lan)
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reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
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ew32(RFCTL, reg);
3627+
3628+
/* Enable ECC on Lynxpoint */
3629+
if (hw->mac.type == e1000_pch_lpt) {
3630+
reg = er32(PBECCSTS);
3631+
reg |= E1000_PBECCSTS_ECC_ENABLE;
3632+
ew32(PBECCSTS, reg);
3633+
3634+
reg = er32(CTRL);
3635+
reg |= E1000_CTRL_MEHE;
3636+
ew32(CTRL, reg);
3637+
}
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}
36283639

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/**

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