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author
olevole
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import gvtd patches
1 parent e131dd8 commit b1d3d24

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6 files changed

+605
-2
lines changed

6 files changed

+605
-2
lines changed

‎bin/cbsdsh/about.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
#define VERSION "14.2.1"
1+
#define VERSION "14.2.2a"

‎cbsd.conf

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ unset oarch over ostable arch target_arch ver stable
1818

1919
# Version
2020
product="CBSD"
21-
myversion="14.2.1"
21+
myversion="14.2.2a"
2222

2323
# CBSD distribution path
2424
distdir="/usr/local/cbsd"

‎upgrade/patch/gvtd-15.0/patch-15x-sys-x86-pci-pci_early_quirks.c

Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,70 @@
1+
--- pci_early_quirks.c.orig 2024-12-15 20:23:31.796640000 +0000
2+
+++ pci_early_quirks.c 2024-12-15 21:52:35.393998000 +0000
3+
@@ -64,6 +64,15 @@
4+
"Size of the intel graphics stolen memory.");
5+
6+
/*
7+
+ * The sysctl value of the Intel graphics generation isn't fully accurate
8+
+ * because it doesn't have to. It's only used by bhyve to check for Intel
9+
+ * graphics gen 11 and above.
10+
+ */
11+
+u_int intel_graphics_gen = 0;
12+
+SYSCTL_UINT(_hw, OID_AUTO, intel_graphics_gen, CTLFLAG_RD, &intel_graphics_gen,
13+
+ 0, "Generation of the intel graphics device.");
14+
+
15+
+/*
16+
* Intel early quirks functions
17+
*/
18+
static vm_paddr_t
19+
@@ -193,36 +202,43 @@
20+
struct intel_stolen_ops {
21+
vm_paddr_t (*base)(int domain, int bus, int slot, int func);
22+
vm_paddr_t (*size)(int domain, int bus, int slot, int func);
23+
+ u_int gen;
24+
};
25+
26+
static const struct intel_stolen_ops intel_stolen_ops_gen3 = {
27+
.base = intel_stolen_base_gen3,
28+
.size = intel_stolen_size_gen3,
29+
+ .gen = 3,
30+
};
31+
32+
static const struct intel_stolen_ops intel_stolen_ops_gen6 = {
33+
.base = intel_stolen_base_gen3,
34+
.size = intel_stolen_size_gen6,
35+
+ .gen = 6,
36+
};
37+
38+
static const struct intel_stolen_ops intel_stolen_ops_gen8 = {
39+
.base = intel_stolen_base_gen3,
40+
.size = intel_stolen_size_gen8,
41+
+ .gen = 8,
42+
};
43+
44+
static const struct intel_stolen_ops intel_stolen_ops_gen9 = {
45+
.base = intel_stolen_base_gen3,
46+
.size = intel_stolen_size_gen9,
47+
+ .gen = 9,
48+
};
49+
50+
static const struct intel_stolen_ops intel_stolen_ops_chv = {
51+
.base = intel_stolen_base_gen3,
52+
.size = intel_stolen_size_chv,
53+
+ .gen = 3,
54+
};
55+
56+
static const struct intel_stolen_ops intel_stolen_ops_gen11 = {
57+
.base = intel_stolen_base_gen11,
58+
.size = intel_stolen_size_gen9,
59+
+ .gen = 11,
60+
};
61+
62+
static const struct pci_device_id intel_ids[] = {
63+
@@ -306,6 +322,7 @@
64+
ops = intel_ids[i].data;
65+
intel_graphics_stolen_base = ops->base(domain, bus, slot, func);
66+
intel_graphics_stolen_size = ops->size(domain, bus, slot, func);
67+
+ intel_graphics_gen = ops->gen;
68+
break;
69+
}
70+

‎upgrade/patch/gvtd-15.0/patch-15x-usr-sbin-bhyve-pci_passthru.c

Lines changed: 251 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,251 @@
1+
--- pci_passthru.c.orig 2024-12-16 14:36:36.044189000 +0300
2+
+++ pci_passthru.c 2024-12-17 01:14:52.899198000 +0300
3+
@@ -72,12 +72,20 @@
4+
#define MSIX_TABLE_COUNT(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1)
5+
#define MSIX_CAPLEN 12
6+
7+
-#define PASSTHRU_MMIO_MAX 2
8+
+#define PASSTHRU_MMIO_MAX 3
9+
10+
static int pcifd = -1;
11+
12+
SET_DECLARE(passthru_dev_set, struct passthru_dev);
13+
14+
+struct passthru_bar_handler {
15+
+ TAILQ_ENTRY(passthru_bar_handler) chain;
16+
+ vm_offset_t off;
17+
+ vm_size_t len;
18+
+ passthru_read_handler read;
19+
+ passthru_write_handler write;
20+
+};
21+
+
22+
struct passthru_softc {
23+
struct pci_devinst *psc_pi;
24+
/* ROM is handled like a BAR */
25+
@@ -95,6 +103,8 @@
26+
struct passthru_mmio_mapping psc_mmio_map[PASSTHRU_MMIO_MAX];
27+
cfgread_handler psc_pcir_rhandler[PCI_REGMAX + 1];
28+
cfgwrite_handler psc_pcir_whandler[PCI_REGMAX + 1];
29+
+ TAILQ_HEAD(,
30+
+ passthru_bar_handler) psc_bar_handler[PCI_BARMAX_WITH_ROM + 1];
31+
};
32+
33+
static int
34+
@@ -694,7 +704,46 @@
35+
36+
return (0);
37+
}
38+
+
39+
+int
40+
+passthru_set_bar_handler(struct passthru_softc *sc, int baridx, vm_offset_t off,
41+
+ vm_size_t len, passthru_read_handler rhandler,
42+
+ passthru_write_handler whandler)
43+
+{
44+
+ struct passthru_bar_handler *handler_new;
45+
+ struct passthru_bar_handler *handler;
46+
+
47+
+ assert(sc->psc_bar[baridx].type == PCIBAR_IO ||
48+
+ sc->psc_bar[baridx].type == PCIBAR_MEM32 ||
49+
+ sc->psc_bar[baridx].type == PCIBAR_MEM64);
50+
+ assert(sc->psc_bar[baridx].size > off + len);
51+
+ assert(off < off + len);
52+
53+
+ handler_new = malloc(sizeof(struct passthru_bar_handler));
54+
+ if (handler_new == NULL) {
55+
+ return (ENOMEM);
56+
+ }
57+
+
58+
+ handler_new->off = off;
59+
+ handler_new->len = len;
60+
+ handler_new->read = rhandler;
61+
+ handler_new->write = whandler;
62+
+
63+
+ TAILQ_FOREACH (handler, &sc->psc_bar_handler[baridx], chain) {
64+
+ if (handler->off < handler_new->off) {
65+
+ assert(handler->off + handler->len < handler_new->off);
66+
+ continue;
67+
+ }
68+
+ assert(handler->off > handler_new->off + handler_new->len);
69+
+ TAILQ_INSERT_BEFORE(handler, handler_new, chain);
70+
+ return (0);
71+
+ }
72+
+
73+
+ TAILQ_INSERT_TAIL(&sc->psc_bar_handler[baridx], handler_new, chain);
74+
+
75+
+ return (0);
76+
+}
77+
+
78+
static int
79+
passthru_legacy_config(nvlist_t *nvl, const char *opts)
80+
{
81+
@@ -900,6 +949,9 @@
82+
83+
pi->pi_arg = sc;
84+
sc->psc_pi = pi;
85+
+
86+
+ for (uint8_t i = 0; i < PCI_BARMAX_WITH_ROM + 1; ++i)
87+
+ TAILQ_INIT(&sc->psc_bar_handler[i]);
88+
89+
/* initialize config space */
90+
if ((error = cfginit(pi, bus, slot, func)) != 0)
91+
@@ -1118,6 +1170,7 @@
92+
uint64_t value)
93+
{
94+
struct passthru_softc *sc;
95+
+ struct passthru_bar_handler *handler;
96+
struct pci_bar_ioreq pio;
97+
98+
sc = pi->pi_arg;
99+
@@ -1125,9 +1178,16 @@
100+
if (baridx == pci_msix_table_bar(pi)) {
101+
msix_table_write(sc, offset, size, value);
102+
} else {
103+
- assert(pi->pi_bar[baridx].type == PCIBAR_IO);
104+
assert(size == 1 || size == 2 || size == 4);
105+
- assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX);
106+
+
107+
+ TAILQ_FOREACH(handler, &sc->psc_bar_handler[baridx], chain) {
108+
+ if (handler->off <= offset &&
109+
+ offset + size <= handler->off + handler->len) {
110+
+ handler->write(pi, offset - handler->off, size,
111+
+ value);
112+
+ return;
113+
+ }
114+
+ }
115+
116+
bzero(&pio, sizeof(pio));
117+
pio.pbi_sel = sc->psc_sel;
118+
@@ -1145,6 +1205,7 @@
119+
passthru_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
120+
{
121+
struct passthru_softc *sc;
122+
+ struct passthru_bar_handler *handler;
123+
struct pci_bar_ioreq pio;
124+
uint64_t val;
125+
126+
@@ -1153,10 +1214,16 @@
127+
if (baridx == pci_msix_table_bar(pi)) {
128+
val = msix_table_read(sc, offset, size);
129+
} else {
130+
- assert(pi->pi_bar[baridx].type == PCIBAR_IO);
131+
assert(size == 1 || size == 2 || size == 4);
132+
- assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX);
133+
134+
+ TAILQ_FOREACH(handler, &sc->psc_bar_handler[baridx], chain) {
135+
+ if (handler->off <= offset &&
136+
+ offset + size <= handler->off + handler->len) {
137+
+ handler->read(pi, offset - handler->off, size, &val);
138+
+ return (val);
139+
+ }
140+
+ }
141+
+
142+
bzero(&pio, sizeof(pio));
143+
pio.pbi_sel = sc->psc_sel;
144+
pio.pbi_op = PCIBARIO_READ;
145+
@@ -1207,47 +1274,84 @@
146+
address += table_offset + table_size;
147+
if (!enabled) {
148+
if (vm_unmap_pptdev_mmio(pi->pi_vmctx,
149+
- sc->psc_sel.pc_bus,
150+
- sc->psc_sel.pc_dev,
151+
- sc->psc_sel.pc_func, address,
152+
- remaining) != 0)
153+
+ sc->psc_sel.pc_bus,
154+
+ sc->psc_sel.pc_dev,
155+
+ sc->psc_sel.pc_func, address,
156+
+ remaining) != 0)
157+
warnx("pci_passthru: unmap_pptdev_mmio failed");
158+
} else {
159+
if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
160+
- sc->psc_sel.pc_dev,
161+
- sc->psc_sel.pc_func, address,
162+
- remaining,
163+
- sc->psc_bar[baridx].addr +
164+
- table_offset + table_size) != 0)
165+
+ sc->psc_sel.pc_dev,
166+
+ sc->psc_sel.pc_func, address,
167+
+ remaining,
168+
+ sc->psc_bar[baridx].addr +
169+
+ table_offset + table_size) != 0)
170+
warnx("pci_passthru: map_pptdev_mmio failed");
171+
}
172+
}
173+
}
174+
175+
-static void
176+
-passthru_mmio_addr(struct pci_devinst *pi, int baridx, int enabled,
177+
- uint64_t address)
178+
+static int
179+
+passthru_mmio_map(struct pci_devinst *pi, int baridx, int enabled,
180+
+ uint64_t address, uint64_t off, uint64_t len)
181+
{
182+
- struct passthru_softc *sc;
183+
+ struct passthru_softc *sc = pi->pi_arg;
184+
185+
- sc = pi->pi_arg;
186+
if (!enabled) {
187+
if (vm_unmap_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
188+
- sc->psc_sel.pc_dev,
189+
- sc->psc_sel.pc_func, address,
190+
- sc->psc_bar[baridx].size) != 0)
191+
- warnx("pci_passthru: unmap_pptdev_mmio failed");
192+
+ sc->psc_sel.pc_dev, sc->psc_sel.pc_func, address + off,
193+
+ len) != 0) {
194+
+ warnx("pci_passthru: unmap_pptdev_mmio failed");
195+
+ return (-1);
196+
+ }
197+
} else {
198+
if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
199+
- sc->psc_sel.pc_dev,
200+
- sc->psc_sel.pc_func, address,
201+
- sc->psc_bar[baridx].size,
202+
- sc->psc_bar[baridx].addr) != 0)
203+
+ sc->psc_sel.pc_dev, sc->psc_sel.pc_func, address + off,
204+
+ len, sc->psc_bar[baridx].addr + off) != 0) {
205+
warnx("pci_passthru: map_pptdev_mmio failed");
206+
+ return (-1);
207+
+ }
208+
}
209+
+
210+
+ return (0);
211+
}
212+
213+
static void
214+
+passthru_mmio_addr(struct pci_devinst *pi, int baridx, int enabled,
215+
+ uint64_t address)
216+
+{
217+
+ struct passthru_softc *sc;
218+
+ struct passthru_bar_handler *handler;
219+
+ uint64_t off;
220+
+
221+
+ sc = pi->pi_arg;
222+
+
223+
+ off = 0;
224+
+
225+
+ /* The queue is sorted by offset in ascending order. */
226+
+ TAILQ_FOREACH(handler, &sc->psc_bar_handler[baridx], chain) {
227+
+ uint64_t handler_off = rounddown2(handler->off, PAGE_SIZE);
228+
+ uint64_t handler_end = roundup2(handler->off + handler->len,
229+
+ PAGE_SIZE);
230+
+
231+
+ /*
232+
+ * When two handler point to the same page, handler_off can be
233+
+ * lower than off. That's fine because we have nothing to do in
234+
+ * that case.
235+
+ */
236+
+ if (handler_off > off) {
237+
+ passthru_mmio_map(pi, baridx, enabled, address, off,
238+
+ handler_off - off);
239+
+ }
240+
+
241+
+ off = handler_end;
242+
+ }
243+
+
244+
+ passthru_mmio_map(pi, baridx, enabled, address, off,
245+
+ sc->psc_bar[baridx].size - off);
246+
+}
247+
+
248+
+static void
249+
passthru_addr_rom(struct pci_devinst *const pi, const int idx,
250+
const int enabled)
251+
{

‎upgrade/patch/gvtd-15.0/patch-15x-usr-sbin-bhyve-pci_passthru.h

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
--- pci_passthru.h.orig 2024-12-16 14:36:36.044279000 +0300
2+
+++ pci_passthru.h 2024-12-16 14:45:20.830669000 +0300
3+
@@ -35,6 +35,10 @@
4+
struct pci_devinst *pi, int coff, int bytes, uint32_t *rv);
5+
typedef int (*cfgwrite_handler)(struct passthru_softc *sc,
6+
struct pci_devinst *pi, int coff, int bytes, uint32_t val);
7+
+typedef int (*passthru_read_handler)(struct pci_devinst *pi, uint64_t off,
8+
+ uint64_t size, uint64_t *rv);
9+
+typedef int (*passthru_write_handler)(struct pci_devinst *pi, uint64_t off,
10+
+ uint64_t size, uint64_t val);
11+
12+
uint32_t pci_host_read_config(const struct pcisel *sel, long reg, int width);
13+
void pci_host_write_config(const struct pcisel *sel, long reg, int width,
14+
@@ -49,3 +53,6 @@
15+
struct pcisel *passthru_get_sel(struct passthru_softc *sc);
16+
int set_pcir_handler(struct passthru_softc *sc, int reg, int len,
17+
cfgread_handler rhandler, cfgwrite_handler whandler);
18+
+int passthru_set_bar_handler(struct passthru_softc *sc, int baridx,
19+
+ vm_offset_t off, vm_size_t len, passthru_read_handler rhandler,
20+
+ passthru_write_handler whandler);

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