Extended yield() support to Stream, analog, Serial, Audio.

cmaglie · cmaglie · commit d9c6e10d8272 · 2012-11-12T16:46:42.000+01:00
diff --git a/hardware/arduino/avr/cores/arduino/HardwareSerial.cpp b/hardware/arduino/avr/cores/arduino/HardwareSerial.cpp
@@ -449,7 +449,8 @@ int HardwareSerial::read(void)
 void HardwareSerial::flush()
 {
   // UDR is kept full while the buffer is not empty, so TXC triggers when EMPTY && SENT
-  while (transmitting && ! (*_ucsra & _BV(TXC0)));
+  while (transmitting && ! (*_ucsra & _BV(TXC0)))
+    yield();
   transmitting = false;
 }
 
@@ -461,7 +462,7 @@ size_t HardwareSerial::write(uint8_t c)
   // wait for the interrupt handler to empty it a bit
   // ???: return 0 here instead?
   while (i == _tx_buffer->tail)
-    ;
+    yield();
 	
   _tx_buffer->buffer[_tx_buffer->head] = c;
   _tx_buffer->head = i;
diff --git a/hardware/arduino/avr/cores/arduino/Stream.cpp b/hardware/arduino/avr/cores/arduino/Stream.cpp
@@ -34,6 +34,7 @@ int Stream::timedRead()
   do {
     c = read();
     if (c >= 0) return c;
+    yield();
   } while(millis() - _startMillis < _timeout);
   return -1;     // -1 indicates timeout
 }
@@ -46,6 +47,7 @@ int Stream::timedPeek()
   do {
     c = peek();
     if (c >= 0) return c;
+    yield();
   } while(millis() - _startMillis < _timeout);
   return -1;     // -1 indicates timeout
 }
diff --git a/hardware/arduino/avr/cores/arduino/wiring_analog.c b/hardware/arduino/avr/cores/arduino/wiring_analog.c
@@ -75,7 +75,8 @@ int analogRead(uint8_t pin)
 	sbi(ADCSRA, ADSC);
 
 	// ADSC is cleared when the conversion finishes
-	while (bit_is_set(ADCSRA, ADSC));
+	while (bit_is_set(ADCSRA, ADSC))
+		yield();
 
 	// we have to read ADCL first; doing so locks both ADCL
 	// and ADCH until ADCH is read.  reading ADCL second would
diff --git a/hardware/arduino/sam/cores/arduino/Stream.cpp b/hardware/arduino/sam/cores/arduino/Stream.cpp
@@ -34,6 +34,7 @@ int Stream::timedRead()
   do {
     c = read();
     if (c >= 0) return c;
+    yield();
   } while(millis() - _startMillis < _timeout);
   return -1;     // -1 indicates timeout
 }
@@ -46,6 +47,7 @@ int Stream::timedPeek()
   do {
     c = peek();
     if (c >= 0) return c;
+    yield();
   } while(millis() - _startMillis < _timeout);
   return -1;     // -1 indicates timeout
 }
diff --git a/hardware/arduino/sam/cores/arduino/UARTClass.cpp b/hardware/arduino/sam/cores/arduino/UARTClass.cpp
@@ -104,14 +104,14 @@ void UARTClass::flush( void )
 {
   // Wait for transmission to complete
   while ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY)
-    ;
+    yield();
 }
 
 size_t UARTClass::write( const uint8_t uc_data )
 {
   // Check if the transmitter is ready
   while ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY)
-    ;
+    yield();
 
   // Send character
   _pUart->UART_THR = uc_data;
diff --git a/hardware/arduino/sam/cores/arduino/USARTClass.cpp b/hardware/arduino/sam/cores/arduino/USARTClass.cpp
@@ -105,14 +105,14 @@ void USARTClass::flush( void )
 {
   // Wait for transmission to complete
   while ((_pUsart->US_CSR & US_CSR_TXRDY) != US_CSR_TXRDY)
-	;
+	yield();
 }
 
 size_t USARTClass::write( const uint8_t uc_data )
 {
   // Check if the transmitter is ready
   while ((_pUsart->US_CSR & US_CSR_TXRDY) != US_CSR_TXRDY)
-    ;
+    yield();
 
   // Send character
   _pUsart->US_THR = uc_data ;
diff --git a/hardware/arduino/sam/cores/arduino/syscalls_sam3.c b/hardware/arduino/sam/cores/arduino/syscalls_sam3.c
@@ -113,7 +113,7 @@ extern int _write( int file, char *ptr, int len )
 
 		// Check if the transmitter is ready
 		  while ((UART->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY)
-			;
+			yield();
 
 		  // Send character
 		  UART->UART_THR = *ptr;
diff --git a/hardware/arduino/sam/libraries/Audio/Audio.cpp b/hardware/arduino/sam/libraries/Audio/Audio.cpp
@@ -54,7 +54,7 @@ size_t AudioClass::write(const uint32_t *data, size_t size) {
 		if (next == half || next == last) {
 			enqueue();
 			while (next == running)
-				;
+				yield();
 		}
 	}
 

Original file line number	Diff line number	Diff line change
`@@ -104,14 +104,14 @@ void UARTClass::flush( void )`
`104`	`104`	`{`
`105`	`105`	`// Wait for transmission to complete`
`106`	`106`	`while ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY)`
`107`		`- ;`
	`107`	`+ yield();`
`108`	`108`	`}`
`109`	`109`
`110`	`110`	`size_t UARTClass::write( const uint8_t uc_data )`
`111`	`111`	`{`
`112`	`112`	`// Check if the transmitter is ready`
`113`	`113`	`while ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY)`
`114`		`- ;`
	`114`	`+ yield();`
`115`	`115`
`116`	`116`	`// Send character`
`117`	`117`	`_pUart->UART_THR = uc_data;`
Original file line number	Diff line number	Diff line change
`@@ -105,14 +105,14 @@ void USARTClass::flush( void )`
`105`	`105`	`{`
`106`	`106`	`// Wait for transmission to complete`
`107`	`107`	`while ((_pUsart->US_CSR & US_CSR_TXRDY) != US_CSR_TXRDY)`
`108`		`- ;`
	`108`	`+ yield();`
`109`	`109`	`}`
`110`	`110`
`111`	`111`	`size_t USARTClass::write( const uint8_t uc_data )`
`112`	`112`	`{`
`113`	`113`	`// Check if the transmitter is ready`
`114`	`114`	`while ((_pUsart->US_CSR & US_CSR_TXRDY) != US_CSR_TXRDY)`
`115`		`- ;`
	`115`	`+ yield();`
`116`	`116`
`117`	`117`	`// Send character`
`118`	`118`	`_pUsart->US_THR = uc_data ;`
Original file line number	Diff line number	Diff line change
`@@ -54,7 +54,7 @@ size_t AudioClass::write(const uint32_t *data, size_t size) {`
`54`	`54`	`if (next == half \|\| next == last) {`
`55`	`55`	`enqueue();`
`56`	`56`	`while (next == running)`
`57`		`- ;`
	`57`	`+ yield();`
`58`	`58`	`}`
`59`	`59`	`}`
`60`	`60`