@@ -45,29 +45,24 @@ struct task_struct *_current_task[NR_CPUS]; /* For stack switching */
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struct cpuinfo_arc cpuinfo_arc700 [NR_CPUS ];
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- static const struct id_to_str arc_cpu_rel [] = {
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+ static const struct id_to_str arc_legacy_rel [] = {
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+ /* ID.ARCVER, Release */
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#ifdef CONFIG_ISA_ARCOMPACT
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- { 0x34 , "R4.10" },
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- { 0x35 , "R4.11" },
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+ { 0x34 , "R4.10" },
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+ { 0x35 , "R4.11" },
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#else
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- { 0x51 , "R2.0" },
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- { 0x52 , "R2.1" },
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- { 0x53 , "R3.0" },
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- { 0x54 , "R3.10a" },
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+ { 0x51 , "R2.0" },
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+ { 0x52 , "R2.1" },
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+ { 0x53 , "R3.0" },
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#endif
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- { 0x00 , NULL }
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+ { 0x00 , NULL }
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};
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- static const struct id_to_str arc_cpu_nm [] = {
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- #ifdef CONFIG_ISA_ARCOMPACT
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- { 0x20 , "ARC 600" },
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- { 0x30 , "ARC 770" }, /* 750 identified seperately */
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- #else
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- { 0x40 , "ARC EM" },
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- { 0x50 , "ARC HS38" },
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- { 0x54 , "ARC HS48" },
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- #endif
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- { 0x00 , "Unknown" }
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+ static const struct id_to_str arc_cpu_rel [] = {
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+ /* UARCH.MAJOR, Release */
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+ { 0 , "R3.10a" },
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+ { 1 , "R3.50a" },
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+ { 0xFF , NULL }
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};
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static void read_decode_ccm_bcr (struct cpuinfo_arc * cpu )
@@ -117,31 +112,72 @@ static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
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}
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}
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+ static void decode_arc_core (struct cpuinfo_arc * cpu )
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+ {
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+ struct bcr_uarch_build_arcv2 uarch ;
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+ const struct id_to_str * tbl ;
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+
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+ /*
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+ * Up until (including) the first core4 release (0x54) things were
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+ * simple: AUX IDENTITY.ARCVER was sufficient to identify arc family
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+ * and release: 0x50 to 0x53 was HS38, 0x54 was HS48 (dual issue)
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+ */
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+
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+ if (cpu -> core .family < 0x54 ) { /* includes arc700 */
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+
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+ for (tbl = & arc_legacy_rel [0 ]; tbl -> id != 0 ; tbl ++ ) {
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+ if (cpu -> core .family == tbl -> id ) {
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+ cpu -> release = tbl -> str ;
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+ break ;
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+ }
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+ }
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+
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+ if (is_isa_arcompact ())
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+ cpu -> name = "ARC700" ;
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+ else if (tbl -> str )
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+ cpu -> name = "HS38" ;
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+ else
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+ cpu -> name = cpu -> release = "Unknown" ;
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+
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+ return ;
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+ }
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+
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+ /*
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+ * However the subsequent HS release (same 0x54) allow HS38 or HS48
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+ * configurations and encode this info in a different BCR.
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+ * The BCR was introduced in 0x54 so can't be read unconditionally.
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+ */
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+
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+ READ_BCR (ARC_REG_MICRO_ARCH_BCR , uarch );
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+
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+ if (uarch .prod == 4 ) {
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+ cpu -> name = "HS48" ;
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+ cpu -> extn .dual = 1 ;
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+
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+ } else {
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+ cpu -> name = "HS38" ;
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+ }
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+
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+ for (tbl = & arc_cpu_rel [0 ]; tbl -> id != 0xFF ; tbl ++ ) {
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+ if (uarch .maj == tbl -> id ) {
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+ cpu -> release = tbl -> str ;
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+ break ;
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+ }
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+ }
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+ }
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+
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static void read_arc_build_cfg_regs (void )
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{
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struct bcr_timer timer ;
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struct bcr_generic bcr ;
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struct cpuinfo_arc * cpu = & cpuinfo_arc700 [smp_processor_id ()];
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- const struct id_to_str * tbl ;
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struct bcr_isa_arcv2 isa ;
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struct bcr_actionpoint ap ;
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FIX_PTR (cpu );
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READ_BCR (AUX_IDENTITY , cpu -> core );
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-
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- for (tbl = & arc_cpu_rel [0 ]; tbl -> id != 0 ; tbl ++ ) {
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- if (cpu -> core .family == tbl -> id ) {
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- cpu -> details = tbl -> str ;
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- break ;
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- }
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- }
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-
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- for (tbl = & arc_cpu_nm [0 ]; tbl -> id != 0 ; tbl ++ ) {
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- if ((cpu -> core .family & 0xF4 ) == tbl -> id )
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- break ;
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- }
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- cpu -> name = tbl -> str ;
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+ decode_arc_core (cpu );
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READ_BCR (ARC_REG_TIMERS_BCR , timer );
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cpu -> extn .timer0 = timer .t0 ;
@@ -199,30 +235,12 @@ static void read_arc_build_cfg_regs(void)
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cpu -> bpu .num_pred = 2048 << bpu .pte ;
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cpu -> bpu .ret_stk = 4 << bpu .rse ;
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- if (cpu -> core .family >= 0x54 ) {
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-
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- struct bcr_uarch_build_arcv2 uarch ;
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-
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- /*
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- * The first 0x54 core (uarch maj:min 0:1 or 0:2) was
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- * dual issue only (HS4x). But next uarch rev (1:0)
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- * allows it be configured for single issue (HS3x)
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- * Ensure we fiddle with dual issue only on HS4x
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- */
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- READ_BCR (ARC_REG_MICRO_ARCH_BCR , uarch );
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+ /* if dual issue hardware, is it enabled ? */
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+ if (cpu -> extn .dual ) {
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+ unsigned int exec_ctrl ;
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- if (uarch .prod == 4 ) {
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- unsigned int exec_ctrl ;
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-
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- /* dual issue hardware always present */
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- cpu -> extn .dual = 1 ;
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-
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- READ_BCR (AUX_EXEC_CTRL , exec_ctrl );
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-
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- /* dual issue hardware enabled ? */
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- cpu -> extn .dual_enb = !(exec_ctrl & 1 );
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-
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- }
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+ READ_BCR (AUX_EXEC_CTRL , exec_ctrl );
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+ cpu -> extn .dual_enb = !(exec_ctrl & 1 );
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}
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}
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@@ -273,7 +291,7 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
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core -> family , core -> cpu_id , core -> chip_id );
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n += scnprintf (buf + n , len - n , "processor [%d]\t: %s %s (%s ISA) %s%s%s\n" ,
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- cpu_id , cpu -> name , cpu -> details ,
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+ cpu_id , cpu -> name , cpu -> release ,
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is_isa_arcompact () ? "ARCompact" : "ARCv2" ,
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IS_AVAIL1 (cpu -> isa .be , "[Big-Endian]" ),
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IS_AVAIL3 (cpu -> extn .dual , cpu -> extn .dual_enb , " Dual-Issue " ));
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