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vineetgarcvineetgarc
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ARCv2: boot log: refurbish HS core/release identification
HS core names and releases have so far been identified based solely on IDENTIFY.ARCVER field. With the future HS releases this will not be sufficient as same ARCVER 0x54 could be an HS38 or HS48. So rewrite the code to use a new BCR to identify the cores properly. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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+75
-57
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2 files changed

+75
-57
lines changed

‎arch/arc/include/asm/arcregs.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -313,7 +313,7 @@ struct cpuinfo_arc {
313313
struct cpuinfo_arc_bpu bpu;
314314
struct bcr_identity core;
315315
struct bcr_isa_arcv2 isa;
316-
const char *details, *name;
316+
const char *release, *name;
317317
unsigned int vec_base;
318318
struct cpuinfo_arc_ccm iccm, dccm;
319319
struct {

‎arch/arc/kernel/setup.c

Lines changed: 74 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -45,29 +45,24 @@ struct task_struct *_current_task[NR_CPUS]; /* For stack switching */
4545

4646
struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
4747

48-
static const struct id_to_str arc_cpu_rel[] = {
48+
static const struct id_to_str arc_legacy_rel[] = {
49+
/* ID.ARCVER, Release */
4950
#ifdef CONFIG_ISA_ARCOMPACT
50-
{ 0x34, "R4.10"},
51-
{ 0x35, "R4.11"},
51+
{ 0x34, "R4.10"},
52+
{ 0x35, "R4.11"},
5253
#else
53-
{ 0x51, "R2.0" },
54-
{ 0x52, "R2.1" },
55-
{ 0x53, "R3.0" },
56-
{ 0x54, "R3.10a" },
54+
{ 0x51, "R2.0" },
55+
{ 0x52, "R2.1" },
56+
{ 0x53, "R3.0" },
5757
#endif
58-
{ 0x00, NULL }
58+
{ 0x00, NULL }
5959
};
6060

61-
static const struct id_to_str arc_cpu_nm[] = {
62-
#ifdef CONFIG_ISA_ARCOMPACT
63-
{ 0x20, "ARC 600" },
64-
{ 0x30, "ARC 770" }, /* 750 identified seperately */
65-
#else
66-
{ 0x40, "ARC EM" },
67-
{ 0x50, "ARC HS38" },
68-
{ 0x54, "ARC HS48" },
69-
#endif
70-
{ 0x00, "Unknown" }
61+
static const struct id_to_str arc_cpu_rel[] = {
62+
/* UARCH.MAJOR, Release */
63+
{ 0, "R3.10a"},
64+
{ 1, "R3.50a"},
65+
{ 0xFF, NULL }
7166
};
7267

7368
static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
@@ -117,31 +112,72 @@ static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
117112
}
118113
}
119114

115+
static void decode_arc_core(struct cpuinfo_arc *cpu)
116+
{
117+
struct bcr_uarch_build_arcv2 uarch;
118+
const struct id_to_str *tbl;
119+
120+
/*
121+
* Up until (including) the first core4 release (0x54) things were
122+
* simple: AUX IDENTITY.ARCVER was sufficient to identify arc family
123+
* and release: 0x50 to 0x53 was HS38, 0x54 was HS48 (dual issue)
124+
*/
125+
126+
if (cpu->core.family < 0x54) { /* includes arc700 */
127+
128+
for (tbl = &arc_legacy_rel[0]; tbl->id != 0; tbl++) {
129+
if (cpu->core.family == tbl->id) {
130+
cpu->release = tbl->str;
131+
break;
132+
}
133+
}
134+
135+
if (is_isa_arcompact())
136+
cpu->name = "ARC700";
137+
else if (tbl->str)
138+
cpu->name = "HS38";
139+
else
140+
cpu->name = cpu->release = "Unknown";
141+
142+
return;
143+
}
144+
145+
/*
146+
* However the subsequent HS release (same 0x54) allow HS38 or HS48
147+
* configurations and encode this info in a different BCR.
148+
* The BCR was introduced in 0x54 so can't be read unconditionally.
149+
*/
150+
151+
READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
152+
153+
if (uarch.prod == 4) {
154+
cpu->name = "HS48";
155+
cpu->extn.dual = 1;
156+
157+
} else {
158+
cpu->name = "HS38";
159+
}
160+
161+
for (tbl = &arc_cpu_rel[0]; tbl->id != 0xFF; tbl++) {
162+
if (uarch.maj == tbl->id) {
163+
cpu->release = tbl->str;
164+
break;
165+
}
166+
}
167+
}
168+
120169
static void read_arc_build_cfg_regs(void)
121170
{
122171
struct bcr_timer timer;
123172
struct bcr_generic bcr;
124173
struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
125-
const struct id_to_str *tbl;
126174
struct bcr_isa_arcv2 isa;
127175
struct bcr_actionpoint ap;
128176

129177
FIX_PTR(cpu);
130178

131179
READ_BCR(AUX_IDENTITY, cpu->core);
132-
133-
for (tbl = &arc_cpu_rel[0]; tbl->id != 0; tbl++) {
134-
if (cpu->core.family == tbl->id) {
135-
cpu->details = tbl->str;
136-
break;
137-
}
138-
}
139-
140-
for (tbl = &arc_cpu_nm[0]; tbl->id != 0; tbl++) {
141-
if ((cpu->core.family & 0xF4) == tbl->id)
142-
break;
143-
}
144-
cpu->name = tbl->str;
180+
decode_arc_core(cpu);
145181

146182
READ_BCR(ARC_REG_TIMERS_BCR, timer);
147183
cpu->extn.timer0 = timer.t0;
@@ -199,30 +235,12 @@ static void read_arc_build_cfg_regs(void)
199235
cpu->bpu.num_pred = 2048 << bpu.pte;
200236
cpu->bpu.ret_stk = 4 << bpu.rse;
201237

202-
if (cpu->core.family >= 0x54) {
203-
204-
struct bcr_uarch_build_arcv2 uarch;
205-
206-
/*
207-
* The first 0x54 core (uarch maj:min 0:1 or 0:2) was
208-
* dual issue only (HS4x). But next uarch rev (1:0)
209-
* allows it be configured for single issue (HS3x)
210-
* Ensure we fiddle with dual issue only on HS4x
211-
*/
212-
READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
238+
/* if dual issue hardware, is it enabled ? */
239+
if (cpu->extn.dual) {
240+
unsigned int exec_ctrl;
213241

214-
if (uarch.prod == 4) {
215-
unsigned int exec_ctrl;
216-
217-
/* dual issue hardware always present */
218-
cpu->extn.dual = 1;
219-
220-
READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
221-
222-
/* dual issue hardware enabled ? */
223-
cpu->extn.dual_enb = !(exec_ctrl & 1);
224-
225-
}
242+
READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
243+
cpu->extn.dual_enb = !(exec_ctrl & 1);
226244
}
227245
}
228246

@@ -273,7 +291,7 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
273291
core->family, core->cpu_id, core->chip_id);
274292

275293
n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n",
276-
cpu_id, cpu->name, cpu->details,
294+
cpu_id, cpu->name, cpu->release,
277295
is_isa_arcompact() ? "ARCompact" : "ARCv2",
278296
IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
279297
IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue "));

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