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EDAC, altera: Merge Stratix10 into the Arria10 SDRAM probe routine
Change Stratix10 regmap to use offsets from a base to match the Arria10 regmap and allow re-use of the Arria10 functions. Only the regmap initialization differs (Arria10 mmio_regmap vs Stratix10 custom regmap). Modify the SDRAM probe function to handle Stratix10. Remove the Stratix10 offset defines if Arria10 can be used. Remove the unused Stratix10 probe function. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: dinguyen@kernel.org Cc: robh+dt@kernel.org Cc: mark.rutland@arm.com Cc: mchehab@kernel.org Cc: devicetree@vger.kernel.org Cc: linux-edac@vger.kernel.org Link: https://lkml.kernel.org/r/1537883342-30180-5-git-send-email-thor.thayer@linux.intel.com
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2 files changed

+14
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lines changed

drivers/edac/altera_edac.c

Lines changed: 9 additions & 267 deletions
Original file line numberDiff line numberDiff line change
@@ -69,25 +69,6 @@ static const struct altr_sdram_prv_data a10_data = {
6969
.ue_set_mask = A10_DIAGINT_TDERRA_MASK,
7070
};
7171

72-
static const struct altr_sdram_prv_data s10_data = {
73-
.ecc_ctrl_offset = S10_ECCCTRL1_OFST,
74-
.ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
75-
.ecc_stat_offset = S10_INTSTAT_OFST,
76-
.ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
77-
.ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
78-
.ecc_saddr_offset = S10_SERRADDR_OFST,
79-
.ecc_daddr_offset = S10_DERRADDR_OFST,
80-
.ecc_irq_en_offset = S10_ERRINTEN_OFST,
81-
.ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
82-
.ecc_irq_clr_offset = S10_INTSTAT_OFST,
83-
.ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
84-
.ecc_cnt_rst_offset = S10_ECCCTRL1_OFST,
85-
.ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
86-
.ce_ue_trgr_offset = S10_DIAGINTTEST_OFST,
87-
.ce_set_mask = A10_DIAGINT_TSERRA_MASK,
88-
.ue_set_mask = A10_DIAGINT_TDERRA_MASK,
89-
};
90-
9172
/*********************** EDAC Memory Controller Functions ****************/
9273

9374
/* The SDRAM controller uses the EDAC Memory Controller framework. */
@@ -239,7 +220,7 @@ static unsigned long get_total_mem(void)
239220
static const struct of_device_id altr_sdram_ctrl_of_match[] = {
240221
{ .compatible = "altr,sdram-edac", .data = &c5_data},
241222
{ .compatible = "altr,sdram-edac-a10", .data = &a10_data},
242-
{ .compatible = "altr,sdram-edac-s10", .data = &s10_data},
223+
{ .compatible = "altr,sdram-edac-s10", .data = &a10_data},
243224
{},
244225
};
245226
MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
@@ -293,6 +274,7 @@ static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
293274
return ret;
294275
}
295276

277+
static int socfpga_is_a10(void);
296278
static int altr_sdram_probe(struct platform_device *pdev)
297279
{
298280
const struct of_device_id *id;
@@ -416,7 +398,7 @@ static int altr_sdram_probe(struct platform_device *pdev)
416398
goto err;
417399

418400
/* Only the Arria10 has separate IRQs */
419-
if (irq2 > 0) {
401+
if (socfpga_is_a10()) {
420402
/* Arria10 specific initialization */
421403
res = a10_init(mc_vbase);
422404
if (res < 0)
@@ -502,8 +484,9 @@ static int s10_protected_reg_write(void *context, unsigned int reg,
502484
unsigned int val)
503485
{
504486
struct arm_smccc_res result;
487+
unsigned long offset = (unsigned long)context;
505488

506-
arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, reg, val, 0, 0,
489+
arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, offset + reg, val, 0, 0,
507490
0, 0, 0, &result);
508491

509492
return (int)result.a0;
@@ -523,254 +506,27 @@ static int s10_protected_reg_read(void *context, unsigned int reg,
523506
unsigned int *val)
524507
{
525508
struct arm_smccc_res result;
509+
unsigned long offset = (unsigned long)context;
526510

527-
arm_smccc_smc(INTEL_SIP_SMC_REG_READ, reg, 0, 0, 0,
511+
arm_smccc_smc(INTEL_SIP_SMC_REG_READ, offset + reg, 0, 0, 0,
528512
0, 0, 0, &result);
529513

530514
*val = (unsigned int)result.a1;
531515

532516
return (int)result.a0;
533517
}
534518

535-
static bool s10_sdram_writeable_reg(struct device *dev, unsigned int reg)
536-
{
537-
switch (reg) {
538-
case S10_ECCCTRL1_OFST:
539-
case S10_ERRINTEN_OFST:
540-
case S10_INTMODE_OFST:
541-
case S10_INTSTAT_OFST:
542-
case S10_DIAGINTTEST_OFST:
543-
case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
544-
case S10_SYSMGR_ECC_INTMASK_SET_OFST:
545-
case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
546-
return true;
547-
}
548-
return false;
549-
}
550-
551-
static bool s10_sdram_readable_reg(struct device *dev, unsigned int reg)
552-
{
553-
switch (reg) {
554-
case S10_ECCCTRL1_OFST:
555-
case S10_ERRINTEN_OFST:
556-
case S10_INTMODE_OFST:
557-
case S10_INTSTAT_OFST:
558-
case S10_DERRADDR_OFST:
559-
case S10_SERRADDR_OFST:
560-
case S10_DIAGINTTEST_OFST:
561-
case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
562-
case S10_SYSMGR_ECC_INTMASK_SET_OFST:
563-
case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
564-
case S10_SYSMGR_ECC_INTSTAT_SERR_OFST:
565-
case S10_SYSMGR_ECC_INTSTAT_DERR_OFST:
566-
return true;
567-
}
568-
return false;
569-
}
570-
571-
static bool s10_sdram_volatile_reg(struct device *dev, unsigned int reg)
572-
{
573-
switch (reg) {
574-
case S10_ECCCTRL1_OFST:
575-
case S10_ERRINTEN_OFST:
576-
case S10_INTMODE_OFST:
577-
case S10_INTSTAT_OFST:
578-
case S10_DERRADDR_OFST:
579-
case S10_SERRADDR_OFST:
580-
case S10_DIAGINTTEST_OFST:
581-
case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
582-
case S10_SYSMGR_ECC_INTMASK_SET_OFST:
583-
case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
584-
case S10_SYSMGR_ECC_INTSTAT_SERR_OFST:
585-
case S10_SYSMGR_ECC_INTSTAT_DERR_OFST:
586-
return true;
587-
}
588-
return false;
589-
}
590-
591519
static const struct regmap_config s10_sdram_regmap_cfg = {
592520
.name = "s10_ddr",
593521
.reg_bits = 32,
594522
.reg_stride = 4,
595523
.val_bits = 32,
596-
.max_register = 0xffffffff,
597-
.writeable_reg = s10_sdram_writeable_reg,
598-
.readable_reg = s10_sdram_readable_reg,
599-
.volatile_reg = s10_sdram_volatile_reg,
524+
.max_register = 0xffd12228,
600525
.reg_read = s10_protected_reg_read,
601526
.reg_write = s10_protected_reg_write,
602527
.use_single_rw = true,
603528
};
604529

605-
static int altr_s10_sdram_probe(struct platform_device *pdev)
606-
{
607-
const struct of_device_id *id;
608-
struct edac_mc_layer layers[2];
609-
struct mem_ctl_info *mci;
610-
struct altr_sdram_mc_data *drvdata;
611-
const struct altr_sdram_prv_data *priv;
612-
struct regmap *regmap;
613-
struct dimm_info *dimm;
614-
u32 read_reg;
615-
int irq, ret = 0;
616-
unsigned long mem_size;
617-
618-
id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
619-
if (!id)
620-
return -ENODEV;
621-
622-
/* Grab specific offsets and masks for Stratix10 */
623-
priv = of_match_node(altr_sdram_ctrl_of_match,
624-
pdev->dev.of_node)->data;
625-
626-
regmap = devm_regmap_init(&pdev->dev, NULL, (void *)priv,
627-
&s10_sdram_regmap_cfg);
628-
if (IS_ERR(regmap))
629-
return PTR_ERR(regmap);
630-
631-
/* Validate the SDRAM controller has ECC enabled */
632-
if (regmap_read(regmap, priv->ecc_ctrl_offset, &read_reg) ||
633-
((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
634-
edac_printk(KERN_ERR, EDAC_MC,
635-
"No ECC/ECC disabled [0x%08X]\n", read_reg);
636-
return -ENODEV;
637-
}
638-
639-
/* Grab memory size from device tree. */
640-
mem_size = get_total_mem();
641-
if (!mem_size) {
642-
edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
643-
return -ENODEV;
644-
}
645-
646-
/* Ensure the SDRAM Interrupt is disabled */
647-
if (regmap_update_bits(regmap, priv->ecc_irq_en_offset,
648-
priv->ecc_irq_en_mask, 0)) {
649-
edac_printk(KERN_ERR, EDAC_MC,
650-
"Error disabling SDRAM ECC IRQ\n");
651-
return -ENODEV;
652-
}
653-
654-
/* Toggle to clear the SDRAM Error count */
655-
if (regmap_update_bits(regmap, priv->ecc_cnt_rst_offset,
656-
priv->ecc_cnt_rst_mask,
657-
priv->ecc_cnt_rst_mask)) {
658-
edac_printk(KERN_ERR, EDAC_MC,
659-
"Error clearing SDRAM ECC count\n");
660-
return -ENODEV;
661-
}
662-
663-
if (regmap_update_bits(regmap, priv->ecc_cnt_rst_offset,
664-
priv->ecc_cnt_rst_mask, 0)) {
665-
edac_printk(KERN_ERR, EDAC_MC,
666-
"Error clearing SDRAM ECC count\n");
667-
return -ENODEV;
668-
}
669-
670-
irq = platform_get_irq(pdev, 0);
671-
if (irq < 0) {
672-
edac_printk(KERN_ERR, EDAC_MC,
673-
"No irq %d in DT\n", irq);
674-
return -ENODEV;
675-
}
676-
677-
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
678-
layers[0].size = 1;
679-
layers[0].is_virt_csrow = true;
680-
layers[1].type = EDAC_MC_LAYER_CHANNEL;
681-
layers[1].size = 1;
682-
layers[1].is_virt_csrow = false;
683-
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
684-
sizeof(struct altr_sdram_mc_data));
685-
if (!mci)
686-
return -ENOMEM;
687-
688-
mci->pdev = &pdev->dev;
689-
drvdata = mci->pvt_info;
690-
drvdata->mc_vbase = regmap;
691-
drvdata->data = priv;
692-
platform_set_drvdata(pdev, mci);
693-
694-
if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
695-
edac_printk(KERN_ERR, EDAC_MC,
696-
"Unable to get managed device resource\n");
697-
ret = -ENOMEM;
698-
goto free;
699-
}
700-
701-
mci->mtype_cap = MEM_FLAG_DDR3;
702-
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
703-
mci->edac_cap = EDAC_FLAG_SECDED;
704-
mci->mod_name = EDAC_MOD_STR;
705-
mci->ctl_name = dev_name(&pdev->dev);
706-
mci->scrub_mode = SCRUB_SW_SRC;
707-
mci->dev_name = dev_name(&pdev->dev);
708-
709-
dimm = *mci->dimms;
710-
dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
711-
dimm->grain = 8;
712-
dimm->dtype = DEV_X8;
713-
dimm->mtype = MEM_DDR3;
714-
dimm->edac_mode = EDAC_SECDED;
715-
716-
ret = edac_mc_add_mc(mci);
717-
if (ret < 0)
718-
goto err;
719-
720-
ret = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
721-
IRQF_SHARED, dev_name(&pdev->dev), mci);
722-
if (ret < 0) {
723-
edac_mc_printk(mci, KERN_ERR,
724-
"Unable to request irq %d\n", irq);
725-
ret = -ENODEV;
726-
goto err2;
727-
}
728-
729-
if (regmap_write(regmap, S10_SYSMGR_ECC_INTMASK_CLR_OFST,
730-
S10_DDR0_IRQ_MASK)) {
731-
edac_printk(KERN_ERR, EDAC_MC,
732-
"Error clearing SDRAM ECC count\n");
733-
ret = -ENODEV;
734-
goto err2;
735-
}
736-
737-
if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
738-
priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
739-
edac_mc_printk(mci, KERN_ERR,
740-
"Error enabling SDRAM ECC IRQ\n");
741-
ret = -ENODEV;
742-
goto err2;
743-
}
744-
745-
altr_sdr_mc_create_debugfs_nodes(mci);
746-
747-
devres_close_group(&pdev->dev, NULL);
748-
749-
return 0;
750-
751-
err2:
752-
edac_mc_del_mc(&pdev->dev);
753-
err:
754-
devres_release_group(&pdev->dev, NULL);
755-
free:
756-
edac_mc_free(mci);
757-
edac_printk(KERN_ERR, EDAC_MC,
758-
"EDAC Probe Failed; Error %d\n", ret);
759-
760-
return ret;
761-
}
762-
763-
static int altr_s10_sdram_remove(struct platform_device *pdev)
764-
{
765-
struct mem_ctl_info *mci = platform_get_drvdata(pdev);
766-
767-
edac_mc_del_mc(&pdev->dev);
768-
edac_mc_free(mci);
769-
platform_set_drvdata(pdev, NULL);
770-
771-
return 0;
772-
}
773-
774530
/************** </Stratix10 EDAC Memory Controller Functions> ***********/
775531

776532
/*
@@ -804,20 +560,6 @@ static struct platform_driver altr_sdram_edac_driver = {
804560

805561
module_platform_driver(altr_sdram_edac_driver);
806562

807-
static struct platform_driver altr_s10_sdram_edac_driver = {
808-
.probe = altr_s10_sdram_probe,
809-
.remove = altr_s10_sdram_remove,
810-
.driver = {
811-
.name = "altr_s10_sdram_edac",
812-
#ifdef CONFIG_PM
813-
.pm = &altr_sdram_pm_ops,
814-
#endif
815-
.of_match_table = altr_sdram_ctrl_of_match,
816-
},
817-
};
818-
819-
module_platform_driver(altr_s10_sdram_edac_driver);
820-
821563
/************************* EDAC Parent Probe *************************/
822564

823565
static const struct of_device_id altr_edac_device_of_match[];
@@ -2163,7 +1905,7 @@ static int s10_edac_dberr_handler(struct notifier_block *this,
21631905
&dberror);
21641906
regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
21651907
if (dberror & S10_DDR0_IRQ_MASK) {
2166-
regmap_read(edac->ecc_mgr_map, S10_DERRADDR_OFST, &err_addr);
1908+
regmap_read(edac->ecc_mgr_map, A10_DERRADDR_OFST, &err_addr);
21671909
regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
21681910
err_addr);
21691911
edac_printk(KERN_ERR, EDAC_MC,

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