arm64: kpti: Whitelist HiSilicon Taishan v110 CPUs

hanjun-guo · ctmarinas · commit 0ecc471a2cb7 · 2019-03-19T14:55:10.000Z
HiSilicon Taishan v110 CPUs didn't implement CSV3 field of the
ID_AA64PFR0_EL1 and are not susceptible to Meltdown, so whitelist
the MIDR in kpti_safe_list[] table.

Signed-off-by: Hanjun Guo &lt;hanjun.guo@linaro.org&gt;
Reviewed-by: John Garry &lt;john.garry@huawei.com&gt;
Reviewed-by: Zhangshaokun &lt;zhangshaokun@hisilicon.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
@@ -963,6 +963,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
+		MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
 		{ /* sentinel */ }
 	};
 	char const *str = "command line option";
