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Merge branches 'clk-imx6-mmdc', 'clk-qcom-krait', 'clk-rockchip' and 'clk-smp2s11-match' into clk-next
 - iMX6 MMDC clks - Qualcomm Krait CPU clk support * clk-imx6-mmdc: clk: imx6q: add mmdc0 ipg clock clk: imx6sl: add mmdc ipg clocks clk: imx6sll: add mmdc1 ipg clock clk: imx6sx: add mmdc1 ipg clock clk: imx6ul: add mmdc1 ipg clock * clk-qcom-krait: clk: qcom: Add safe switch hook for krait mux clocks dt-bindings: clock: Document qcom,krait-cc clk: qcom: Add Krait clock controller driver dt-bindings: arm: Document qcom,kpss-gcc clk: qcom: Add KPSS ACC/GCC driver clk: qcom: Add support for Krait clocks clk: qcom: Add IPQ806X's HFPLLs clk: qcom: Add MSM8960/APQ8064's HFPLLs dt-bindings: clock: Document qcom,hfpll clk: qcom: Add HFPLL driver clk: qcom: Add support for High-Frequency PLLs (HFPLLs) ARM: Add Krait L2 register accessor functions * clk-rockchip: clk: rockchip: Fix static checker warning in rockchip_ddrclk_get_parent call clk: rockchip: use the newly added clock-id for hdmi on RK3066 clk: rockchip: add clock-id for HCLK_HDMI on rk3066 clk: rockchip: fix wrong mmc sample phase shift for rk3328 clk: rockchip: improve rk3288 pll rates for better hdmi output * clk-smp2s11-match: clk: s2mps11: Add used attribute to s2mps11_dt_match clk: s2mps11: Fix matching when built as module and DT node contains compatible
5 parents 1fe7c04 + 341ce35 + 7761272 + 1b4d990 + 9c940bb commit 1578968

36 files changed

+1620
-19
lines changed

‎Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt

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@@ -21,10 +21,29 @@ PROPERTIES
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the register region. An optional second element specifies
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the base address and size of the alias register region.
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: reference to the pll parents.
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- clock-names:
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Usage: required
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Value type: <stringlist>
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Definition: must be "pll8_vote", "pxo".
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- clock-output-names:
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Usage: optional
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Value type: <string>
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Definition: Name of the output clock. Typically acpuX_aux where X is a
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CPU number starting at 0.
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Example:
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clock-controller@2088000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0x02088000 0x1000>,
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<0x02008000 0x1000>;
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clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
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clock-names = "pll8_vote", "pxo";
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clock-output-names = "acpu0_aux";
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};

‎Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt

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Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
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PROPERTIES
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- compatible:
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Usage: required
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Value type: <string>
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Definition: should be one of the following. The generic compatible
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"qcom,kpss-gcc" should also be included.
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"qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
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"qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
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"qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
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"qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: base address and size of the register region
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: reference to the pll parents.
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- clock-names:
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Usage: required
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Value type: <stringlist>
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Definition: must be "pll8_vote", "pxo".
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- clock-output-names:
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Usage: required
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Value type: <string>
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Definition: Name of the output clock. Typically acpu_l2_aux indicating
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an L2 cache auxiliary clock.
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Example:
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l2cc: clock-controller@2011000 {
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compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
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reg = <0x2011000 0x1000>;
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clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
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clock-names = "pll8_vote", "pxo";
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clock-output-names = "acpu_l2_aux";
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};

‎Documentation/devicetree/bindings/clock/qcom,hfpll.txt

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High-Frequency PLL (HFPLL)
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PROPERTIES
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- compatible:
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Usage: required
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Value type: <string>:
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shall contain only one of the following. The generic
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compatible "qcom,hfpll" should be also included.
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"qcom,hfpll-ipq8064", "qcom,hfpll"
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"qcom,hfpll-apq8064", "qcom,hfpll"
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"qcom,hfpll-msm8974", "qcom,hfpll"
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"qcom,hfpll-msm8960", "qcom,hfpll"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: address and size of HPLL registers. An optional second
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element specifies the address and size of the alias
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register region.
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: reference to the xo clock.
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- clock-names:
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Usage: required
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Value type: <stringlist>
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Definition: must be "xo".
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- clock-output-names:
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Usage: required
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Value type: <string>
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Definition: Name of the PLL. Typically hfpllX where X is a CPU number
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starting at 0. Otherwise hfpll_Y where Y is more specific
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such as "l2".
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Example:
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1) An HFPLL for the L2 cache.
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clock-controller@f9016000 {
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compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
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reg = <0xf9016000 0x30>;
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clocks = <&xo_board>;
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clock-names = "xo";
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clock-output-names = "hfpll_l2";
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};
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2) An HFPLL for CPU0. This HFPLL has the alias register region.
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clock-controller@f908a000 {
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compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
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reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
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clocks = <&xo_board>;
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clock-names = "xo";
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clock-output-names = "hfpll0";
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};

‎Documentation/devicetree/bindings/clock/qcom,krait-cc.txt

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Krait Clock Controller
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PROPERTIES
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be one of:
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"qcom,krait-cc-v1"
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"qcom,krait-cc-v2"
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- #clock-cells:
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Usage: required
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Value type: <u32>
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Definition: must be 1
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: reference to the clock parents of hfpll, secondary muxes.
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- clock-names:
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Usage: required
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Value type: <stringlist>
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Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb".
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Example:
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kraitcc: clock-controller {
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compatible = "qcom,krait-cc-v1";
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clocks = <&hfpll0>, <&hfpll1>, <&acpu0_aux>, <&acpu1_aux>, <qsb>;
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clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb";
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#clock-cells = <1>;
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};

‎arch/arm/common/Kconfig

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@@ -7,6 +7,9 @@ config DMABOUNCE
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bool
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select ZONE_DMA
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config KRAIT_L2_ACCESSORS
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bool
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config SHARP_LOCOMO
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bool
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‎arch/arm/common/Makefile

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@@ -7,6 +7,7 @@ obj-y += firmware.o
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obj-$(CONFIG_SA1111) += sa1111.o
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obj-$(CONFIG_DMABOUNCE) += dmabounce.o
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obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o
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obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
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obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
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obj-$(CONFIG_SHARP_SCOOP) += scoop.o

‎arch/arm/common/krait-l2-accessors.c

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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018, The Linux Foundation. All rights reserved.
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#include <linux/spinlock.h>
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#include <linux/export.h>
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#include <asm/barrier.h>
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#include <asm/krait-l2-accessors.h>
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static DEFINE_RAW_SPINLOCK(krait_l2_lock);
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void krait_set_l2_indirect_reg(u32 addr, u32 val)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&krait_l2_lock, flags);
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/*
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* Select the L2 window by poking l2cpselr, then write to the window
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* via l2cpdr.
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*/
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asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr));
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isb();
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asm volatile ("mcr p15, 3, %0, c15, c0, 7 @ l2cpdr" : : "r" (val));
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isb();
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raw_spin_unlock_irqrestore(&krait_l2_lock, flags);
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}
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EXPORT_SYMBOL(krait_set_l2_indirect_reg);
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u32 krait_get_l2_indirect_reg(u32 addr)
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{
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u32 val;
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unsigned long flags;
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raw_spin_lock_irqsave(&krait_l2_lock, flags);
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/*
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* Select the L2 window by poking l2cpselr, then read from the window
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* via l2cpdr.
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*/
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asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr));
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isb();
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asm volatile ("mrc p15, 3, %0, c15, c0, 7 @ l2cpdr" : "=r" (val));
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raw_spin_unlock_irqrestore(&krait_l2_lock, flags);
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return val;
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}
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EXPORT_SYMBOL(krait_get_l2_indirect_reg);

‎arch/arm/include/asm/krait-l2-accessors.h

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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASMARM_KRAIT_L2_ACCESSORS_H
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#define __ASMARM_KRAIT_L2_ACCESSORS_H
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extern void krait_set_l2_indirect_reg(u32 addr, u32 val);
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extern u32 krait_get_l2_indirect_reg(u32 addr);
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#endif

‎drivers/clk/clk-s2mps11.c

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@@ -229,6 +229,36 @@ static const struct platform_device_id s2mps11_clk_id[] = {
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};
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MODULE_DEVICE_TABLE(platform, s2mps11_clk_id);
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#ifdef CONFIG_OF
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/*
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* Device is instantiated through parent MFD device and device matching is done
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* through platform_device_id.
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*
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* However if device's DT node contains proper clock compatible and driver is
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* built as a module, then the *module* matching will be done trough DT aliases.
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* This requires of_device_id table. In the same time this will not change the
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* actual *device* matching so do not add .of_match_table.
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*/
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static const struct of_device_id s2mps11_dt_match[] __used = {
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{
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.compatible = "samsung,s2mps11-clk",
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.data = (void *)S2MPS11X,
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}, {
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.compatible = "samsung,s2mps13-clk",
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.data = (void *)S2MPS13X,
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}, {
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.compatible = "samsung,s2mps14-clk",
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.data = (void *)S2MPS14X,
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}, {
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.compatible = "samsung,s5m8767-clk",
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.data = (void *)S5M8767X,
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}, {
256+
/* Sentinel */
257+
},
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};
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MODULE_DEVICE_TABLE(of, s2mps11_dt_match);
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#endif
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232262
static struct platform_driver s2mps11_clk_driver = {
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.driver = {
234264
.name = "s2mps11-clk",

‎drivers/clk/imx/clk-imx6q.c

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@@ -789,6 +789,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
790790
clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2_flags("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20, CLK_IS_CRITICAL);
791791
clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
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clk[IMX6QDL_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
792793
clk[IMX6QDL_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
793794
clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
794795
clk[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);

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