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paulburtonpaulburton
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MIPS: Delete unused flush_cache_sigtramp()
Commit adcc81f ("MIPS: math-emu: Write-protect delay slot emulation pages") left flush_cache_sigtramp() unused. Delete the dead code. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Davidlohr Bueso <dave@stgolabs.net> Cc: linux-mips@vger.kernel.org
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-183
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6 files changed

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‎arch/mips/include/asm/cacheflush.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,6 @@
2525
*
2626
* MIPS specific flush operations:
2727
*
28-
* - flush_cache_sigtramp() flush signal trampoline
2928
* - flush_icache_all() flush the entire instruction cache
3029
* - flush_data_cache_page() flushes a page from the data cache
3130
* - __flush_icache_user_range(start, end) flushes range of user instructions
@@ -110,7 +109,6 @@ extern void copy_from_user_page(struct vm_area_struct *vma,
110109
struct page *page, unsigned long vaddr, void *dst, const void *src,
111110
unsigned long len);
112111

113-
extern void (*flush_cache_sigtramp)(unsigned long addr);
114112
extern void (*flush_icache_all)(void);
115113
extern void (*local_flush_data_cache_page)(void * addr);
116114
extern void (*flush_data_cache_page)(unsigned long addr);

‎arch/mips/mm/c-octeon.c

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -127,23 +127,6 @@ static void octeon_flush_icache_range(unsigned long start, unsigned long end)
127127
}
128128

129129

130-
/**
131-
* Flush the icache for a trampoline. These are used for interrupt
132-
* and exception hooking.
133-
*
134-
* @addr: Address to flush
135-
*/
136-
static void octeon_flush_cache_sigtramp(unsigned long addr)
137-
{
138-
struct vm_area_struct *vma;
139-
140-
down_read(&current->mm->mmap_sem);
141-
vma = find_vma(current->mm, addr);
142-
octeon_flush_icache_all_cores(vma);
143-
up_read(&current->mm->mmap_sem);
144-
}
145-
146-
147130
/**
148131
* Flush a range out of a vma
149132
*
@@ -289,7 +272,6 @@ void octeon_cache_init(void)
289272
flush_cache_mm = octeon_flush_cache_mm;
290273
flush_cache_page = octeon_flush_cache_page;
291274
flush_cache_range = octeon_flush_cache_range;
292-
flush_cache_sigtramp = octeon_flush_cache_sigtramp;
293275
flush_icache_all = octeon_flush_icache_all;
294276
flush_data_cache_page = octeon_flush_data_cache_page;
295277
flush_icache_range = octeon_flush_icache_range;

‎arch/mips/mm/c-r3k.c

Lines changed: 0 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -274,30 +274,6 @@ static void r3k_flush_data_cache_page(unsigned long addr)
274274
{
275275
}
276276

277-
static void r3k_flush_cache_sigtramp(unsigned long addr)
278-
{
279-
unsigned long flags;
280-
281-
pr_debug("csigtramp[%08lx]\n", addr);
282-
283-
flags = read_c0_status();
284-
285-
write_c0_status(flags&~ST0_IEC);
286-
287-
/* Fill the TLB to avoid an exception with caches isolated. */
288-
asm( "lw\t$0, 0x000(%0)\n\t"
289-
"lw\t$0, 0x004(%0)\n\t"
290-
: : "r" (addr) );
291-
292-
write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
293-
294-
asm( "sb\t$0, 0x000(%0)\n\t"
295-
"sb\t$0, 0x004(%0)\n\t"
296-
: : "r" (addr) );
297-
298-
write_c0_status(flags);
299-
}
300-
301277
static void r3k_flush_kernel_vmap_range(unsigned long vaddr, int size)
302278
{
303279
BUG();
@@ -331,7 +307,6 @@ void r3k_cache_init(void)
331307

332308
__flush_kernel_vmap_range = r3k_flush_kernel_vmap_range;
333309

334-
flush_cache_sigtramp = r3k_flush_cache_sigtramp;
335310
local_flush_data_cache_page = local_r3k_flush_data_cache_page;
336311
flush_data_cache_page = r3k_flush_data_cache_page;
337312

‎arch/mips/mm/c-r4k.c

Lines changed: 0 additions & 116 deletions
Original file line numberDiff line numberDiff line change
@@ -937,119 +937,6 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
937937
}
938938
#endif /* CONFIG_DMA_NONCOHERENT */
939939

940-
struct flush_cache_sigtramp_args {
941-
struct mm_struct *mm;
942-
struct page *page;
943-
unsigned long addr;
944-
};
945-
946-
/*
947-
* While we're protected against bad userland addresses we don't care
948-
* very much about what happens in that case. Usually a segmentation
949-
* fault will dump the process later on anyway ...
950-
*/
951-
static void local_r4k_flush_cache_sigtramp(void *args)
952-
{
953-
struct flush_cache_sigtramp_args *fcs_args = args;
954-
unsigned long addr = fcs_args->addr;
955-
struct page *page = fcs_args->page;
956-
struct mm_struct *mm = fcs_args->mm;
957-
int map_coherent = 0;
958-
void *vaddr;
959-
960-
unsigned long ic_lsize = cpu_icache_line_size();
961-
unsigned long dc_lsize = cpu_dcache_line_size();
962-
unsigned long sc_lsize = cpu_scache_line_size();
963-
964-
/*
965-
* If owns no valid ASID yet, cannot possibly have gotten
966-
* this page into the cache.
967-
*/
968-
if (!has_valid_asid(mm, R4K_HIT))
969-
return;
970-
971-
if (mm == current->active_mm) {
972-
vaddr = NULL;
973-
} else {
974-
/*
975-
* Use kmap_coherent or kmap_atomic to do flushes for
976-
* another ASID than the current one.
977-
*/
978-
map_coherent = (cpu_has_dc_aliases &&
979-
page_mapcount(page) &&
980-
!Page_dcache_dirty(page));
981-
if (map_coherent)
982-
vaddr = kmap_coherent(page, addr);
983-
else
984-
vaddr = kmap_atomic(page);
985-
addr = (unsigned long)vaddr + (addr & ~PAGE_MASK);
986-
}
987-
988-
R4600_HIT_CACHEOP_WAR_IMPL;
989-
if (!cpu_has_ic_fills_f_dc) {
990-
if (dc_lsize)
991-
vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
992-
: protected_writeback_dcache_line(
993-
addr & ~(dc_lsize - 1));
994-
if (!cpu_icache_snoops_remote_store && scache_size)
995-
vaddr ? flush_scache_line(addr & ~(sc_lsize - 1))
996-
: protected_writeback_scache_line(
997-
addr & ~(sc_lsize - 1));
998-
}
999-
if (ic_lsize)
1000-
vaddr ? flush_icache_line(addr & ~(ic_lsize - 1))
1001-
: protected_flush_icache_line(addr & ~(ic_lsize - 1));
1002-
1003-
if (vaddr) {
1004-
if (map_coherent)
1005-
kunmap_coherent();
1006-
else
1007-
kunmap_atomic(vaddr);
1008-
}
1009-
1010-
if (MIPS4K_ICACHE_REFILL_WAR) {
1011-
__asm__ __volatile__ (
1012-
".set push\n\t"
1013-
".set noat\n\t"
1014-
".set "MIPS_ISA_LEVEL"\n\t"
1015-
#ifdef CONFIG_32BIT
1016-
"la $at,1f\n\t"
1017-
#endif
1018-
#ifdef CONFIG_64BIT
1019-
"dla $at,1f\n\t"
1020-
#endif
1021-
"cache %0,($at)\n\t"
1022-
"nop; nop; nop\n"
1023-
"1:\n\t"
1024-
".set pop"
1025-
:
1026-
: "i" (Hit_Invalidate_I));
1027-
}
1028-
if (MIPS_CACHE_SYNC_WAR)
1029-
__asm__ __volatile__ ("sync");
1030-
}
1031-
1032-
static void r4k_flush_cache_sigtramp(unsigned long addr)
1033-
{
1034-
struct flush_cache_sigtramp_args args;
1035-
int npages;
1036-
1037-
down_read(&current->mm->mmap_sem);
1038-
1039-
npages = get_user_pages_fast(addr, 1, 0, &args.page);
1040-
if (npages < 1)
1041-
goto out;
1042-
1043-
args.mm = current->mm;
1044-
args.addr = addr;
1045-
1046-
r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_sigtramp, &args);
1047-
1048-
put_page(args.page);
1049-
out:
1050-
up_read(&current->mm->mmap_sem);
1051-
}
1052-
1053940
static void r4k_flush_icache_all(void)
1054941
{
1055942
if (cpu_has_vtag_icache)
@@ -1978,7 +1865,6 @@ void r4k_cache_init(void)
19781865

19791866
__flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
19801867

1981-
flush_cache_sigtramp = r4k_flush_cache_sigtramp;
19821868
flush_icache_all = r4k_flush_icache_all;
19831869
local_flush_data_cache_page = local_r4k_flush_data_cache_page;
19841870
flush_data_cache_page = r4k_flush_data_cache_page;
@@ -2033,7 +1919,6 @@ void r4k_cache_init(void)
20331919
/* I$ fills from D$ just by emptying the write buffers */
20341920
flush_cache_page = (void *)b5k_instruction_hazard;
20351921
flush_cache_range = (void *)b5k_instruction_hazard;
2036-
flush_cache_sigtramp = (void *)b5k_instruction_hazard;
20371922
local_flush_data_cache_page = (void *)b5k_instruction_hazard;
20381923
flush_data_cache_page = (void *)b5k_instruction_hazard;
20391924
flush_icache_range = (void *)b5k_instruction_hazard;
@@ -2052,7 +1937,6 @@ void r4k_cache_init(void)
20521937
flush_cache_mm = (void *)cache_noop;
20531938
flush_cache_page = (void *)cache_noop;
20541939
flush_cache_range = (void *)cache_noop;
2055-
flush_cache_sigtramp = (void *)cache_noop;
20561940
flush_icache_all = (void *)cache_noop;
20571941
flush_data_cache_page = (void *)cache_noop;
20581942
local_flush_data_cache_page = (void *)cache_noop;

‎arch/mips/mm/c-tx39.c

Lines changed: 0 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -290,25 +290,6 @@ static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
290290
}
291291
}
292292

293-
static void tx39_flush_cache_sigtramp(unsigned long addr)
294-
{
295-
unsigned long ic_lsize = current_cpu_data.icache.linesz;
296-
unsigned long dc_lsize = current_cpu_data.dcache.linesz;
297-
unsigned long config;
298-
unsigned long flags;
299-
300-
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
301-
302-
/* disable icache (set ICE#) */
303-
local_irq_save(flags);
304-
config = read_c0_conf();
305-
write_c0_conf(config & ~TX39_CONF_ICE);
306-
TX39_STOP_STREAMING();
307-
protected_flush_icache_line(addr & ~(ic_lsize - 1));
308-
write_c0_conf(config);
309-
local_irq_restore(flags);
310-
}
311-
312293
static __init void tx39_probe_cache(void)
313294
{
314295
unsigned long config;
@@ -368,7 +349,6 @@ void tx39_cache_init(void)
368349
flush_icache_range = (void *) tx39h_flush_icache_all;
369350
local_flush_icache_range = (void *) tx39h_flush_icache_all;
370351

371-
flush_cache_sigtramp = (void *) tx39h_flush_icache_all;
372352
local_flush_data_cache_page = (void *) tx39h_flush_icache_all;
373353
flush_data_cache_page = (void *) tx39h_flush_icache_all;
374354

@@ -397,7 +377,6 @@ void tx39_cache_init(void)
397377

398378
__flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;
399379

400-
flush_cache_sigtramp = tx39_flush_cache_sigtramp;
401380
local_flush_data_cache_page = local_tx39_flush_data_cache_page;
402381
flush_data_cache_page = tx39_flush_data_cache_page;
403382

‎arch/mips/mm/cache.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,6 @@ void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
4747
EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range);
4848

4949
/* MIPS specific cache operations */
50-
void (*flush_cache_sigtramp)(unsigned long addr);
5150
void (*local_flush_data_cache_page)(void * addr);
5251
void (*flush_data_cache_page)(unsigned long addr);
5352
void (*flush_icache_all)(void);

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