drm/amdgpu/vega20: add CLK base offset

alexdeucher · alexdeucher · commit 3426d66d3e74 · 2018-11-06T16:25:51.000-05:00
In case we need to access CLK registers.

Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
@@ -49,6 +49,7 @@ int vega20_reg_base_init(struct amdgpu_device *adev)
 		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
 		adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
 		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+		adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
 	}
 	return 0;
 }

Original file line number	Diff line number	Diff line change
`@@ -49,6 +49,7 @@ int vega20_reg_base_init(struct amdgpu_device *adev)`
`49`	`49`	`adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));`
`50`	`50`	`adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));`
`51`	`51`	`adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));`
	`52`	`+ adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));`
`52`	`53`	`}`
`53`	`54`	`return 0;`
`54`	`55`	`}`