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torvaldstorvalds
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Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull more timer updates from Thomas Gleixner: "A set of commits for the new C-SKY architecture timers" * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: dt-bindings: timer: gx6605s SOC timer clocksource/drivers/c-sky: Add gx6605s SOC system timer dt-bindings: timer: C-SKY Multi-processor timer clocksource/drivers/c-sky: Add C-SKY SMP timer
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‎Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt

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=================
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gx6605s SOC Timer
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=================
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The timer is used in gx6605s soc as system timer and the driver
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contain clk event and clk source.
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==============================
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timer node bindings definition
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==============================
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Description: Describes gx6605s SOC timer
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PROPERTIES
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- compatible
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Usage: required
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Value type: <string>
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Definition: must be "csky,gx6605s-timer"
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- reg
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Usage: required
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Value type: <u32 u32>
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Definition: <phyaddr size> in soc from cpu view
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- clocks
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Usage: required
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Value type: phandle + clock specifier cells
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Definition: must be input clk node
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- interrupt
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Usage: required
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Value type: <u32>
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Definition: must be timer irq num defined by soc
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Examples:
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---------
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timer0: timer@20a000 {
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compatible = "csky,gx6605s-timer";
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reg = <0x0020a000 0x400>;
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clocks = <&dummy_apb_clk>;
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interrupts = <10>;
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interrupt-parent = <&intc>;
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};

‎Documentation/devicetree/bindings/timer/csky,mptimer.txt

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============================
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C-SKY Multi-processors Timer
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============================
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C-SKY multi-processors timer is designed for C-SKY SMP system and the
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regs is accessed by cpu co-processor 4 registers with mtcr/mfcr.
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- PTIM_CTLR "cr<0, 14>" Control reg to start reset timer.
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- PTIM_TSR "cr<1, 14>" Interrupt cleanup status reg.
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- PTIM_CCVR "cr<3, 14>" Current counter value reg.
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- PTIM_LVR "cr<6, 14>" Window value reg to triger next event.
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==============================
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timer node bindings definition
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==============================
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Description: Describes SMP timer
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PROPERTIES
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- compatible
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Usage: required
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Value type: <string>
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Definition: must be "csky,mptimer"
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- clocks
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Usage: required
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Value type: <node>
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Definition: must be input clk node
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- interrupts
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Usage: required
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Value type: <u32>
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Definition: must be timer irq num defined by soc
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Examples:
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---------
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timer: timer {
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compatible = "csky,mptimer";
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clocks = <&dummy_apb_clk>;
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interrupts = <16>;
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interrupt-parent = <&intc>;
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};

‎drivers/clocksource/Kconfig

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@@ -620,4 +620,22 @@ config RISCV_TIMER
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is accessed via both the SBI and the rdcycle instruction. This is
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required for all RISC-V systems.
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config CSKY_MP_TIMER
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bool "SMP Timer for the C-SKY platform" if COMPILE_TEST
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depends on CSKY
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select TIMER_OF
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help
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Say yes here to enable C-SKY SMP timer driver used for C-SKY SMP
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system.
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csky,mptimer is not only used in SMP system, it also could be used
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single core system. It's not a mmio reg and it use mtcr/mfcr instruction.
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config GX6605S_TIMER
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bool "Gx6605s SOC system timer driver" if COMPILE_TEST
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depends on CSKY
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select CLKSRC_MMIO
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select TIMER_OF
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help
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This option enables support for gx6605s SOC's timer.
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endmenu

‎drivers/clocksource/Makefile

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@@ -79,3 +79,5 @@ obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
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obj-$(CONFIG_X86_NUMACHIP) += numachip.o
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obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o
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obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
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obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o
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obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o

‎drivers/clocksource/timer-gx6605s.c

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// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/sched_clock.h>
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#include "timer-of.h"
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#define CLKSRC_OFFSET 0x40
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#define TIMER_STATUS 0x00
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#define TIMER_VALUE 0x04
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#define TIMER_CONTRL 0x10
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#define TIMER_CONFIG 0x20
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#define TIMER_DIV 0x24
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#define TIMER_INI 0x28
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#define GX6605S_STATUS_CLR BIT(0)
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#define GX6605S_CONTRL_RST BIT(0)
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#define GX6605S_CONTRL_START BIT(1)
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#define GX6605S_CONFIG_EN BIT(0)
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#define GX6605S_CONFIG_IRQ_EN BIT(1)
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static irqreturn_t gx6605s_timer_interrupt(int irq, void *dev)
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{
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struct clock_event_device *ce = dev;
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void __iomem *base = timer_of_base(to_timer_of(ce));
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writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS);
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ce->event_handler(ce);
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return IRQ_HANDLED;
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}
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static int gx6605s_timer_set_oneshot(struct clock_event_device *ce)
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{
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void __iomem *base = timer_of_base(to_timer_of(ce));
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/* reset and stop counter */
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writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
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/* enable with irq and start */
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writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN,
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base + TIMER_CONFIG);
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return 0;
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}
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static int gx6605s_timer_set_next_event(unsigned long delta,
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struct clock_event_device *ce)
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{
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void __iomem *base = timer_of_base(to_timer_of(ce));
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/* use reset to pause timer */
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writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
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/* config next timeout value */
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writel_relaxed(ULONG_MAX - delta, base + TIMER_INI);
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writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
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return 0;
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}
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static int gx6605s_timer_shutdown(struct clock_event_device *ce)
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{
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void __iomem *base = timer_of_base(to_timer_of(ce));
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writel_relaxed(0, base + TIMER_CONTRL);
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writel_relaxed(0, base + TIMER_CONFIG);
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return 0;
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}
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static struct timer_of to = {
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.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
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.clkevt = {
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.rating = 300,
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.features = CLOCK_EVT_FEAT_DYNIRQ |
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CLOCK_EVT_FEAT_ONESHOT,
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.set_state_shutdown = gx6605s_timer_shutdown,
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.set_state_oneshot = gx6605s_timer_set_oneshot,
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.set_next_event = gx6605s_timer_set_next_event,
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.cpumask = cpu_possible_mask,
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},
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.of_irq = {
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.handler = gx6605s_timer_interrupt,
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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},
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};
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static u64 notrace gx6605s_sched_clock_read(void)
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{
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void __iomem *base;
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base = timer_of_base(&to) + CLKSRC_OFFSET;
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return (u64)readl_relaxed(base + TIMER_VALUE);
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}
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static void gx6605s_clkevt_init(void __iomem *base)
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{
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writel_relaxed(0, base + TIMER_DIV);
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writel_relaxed(0, base + TIMER_CONFIG);
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clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 2,
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ULONG_MAX);
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}
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static int gx6605s_clksrc_init(void __iomem *base)
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{
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writel_relaxed(0, base + TIMER_DIV);
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writel_relaxed(0, base + TIMER_INI);
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writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
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writel_relaxed(GX6605S_CONFIG_EN, base + TIMER_CONFIG);
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writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
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sched_clock_register(gx6605s_sched_clock_read, 32, timer_of_rate(&to));
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return clocksource_mmio_init(base + TIMER_VALUE, "gx6605s",
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timer_of_rate(&to), 200, 32, clocksource_mmio_readl_up);
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}
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static int __init gx6605s_timer_init(struct device_node *np)
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{
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int ret;
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/*
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* The timer driver is for nationalchip gx6605s SOC and there are two
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* same timer in gx6605s. We use one for clkevt and another for clksrc.
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*
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* The timer is mmio map to access, so we need give mmio address in dts.
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*
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* It provides a 32bit countup timer and interrupt will be caused by
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* count-overflow.
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* So we need set-next-event by ULONG_MAX - delta in TIMER_INI reg.
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*
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* The counter at 0x0 offset is clock event.
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* The counter at 0x40 offset is clock source.
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* They are the same in hardware, just different used by driver.
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*/
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ret = timer_of_init(np, &to);
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if (ret)
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return ret;
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gx6605s_clkevt_init(timer_of_base(&to));
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return gx6605s_clksrc_init(timer_of_base(&to) + CLKSRC_OFFSET);
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}
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TIMER_OF_DECLARE(csky_gx6605s_timer, "csky,gx6605s-timer", gx6605s_timer_init);

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