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Merge tag 'reset-for-5.0-rc2' of git://git.pengutronix.de/git/pza/linux into fixes
Late reset controller changes for v5.0 This adds missing deassert functionality to the ARC HSDK reset driver, fixes some indentation and grammar issues in the kernel docs, adds a helper to count the number of resets on a device for the non-DT case as well, adds an early reset driver for SoCFPGA and simple reset driver support for Stratix10, and generalizes the uniphier USB3 glue layer reset to also cover AHCI. * tag 'reset-for-5.0-rc2' of git://git.pengutronix.de/git/pza/linux: reset: uniphier-glue: Add AHCI reset control support in glue layer dt-bindings: reset: uniphier: Add AHCI core reset description reset: uniphier-usb3: Rename to reset-uniphier-glue dt-bindings: reset: uniphier: Replace the expression of USB3 with generic peripherals ARM: socfpga: dts: document "altr,stratix10-rst-mgr" binding reset: socfpga: add an early reset driver for SoCFPGA reset: fix null pointer dereference on dev by dev_name reset: Add reset_control_get_count() reset: Improve reset controller kernel docs ARC: HSDK: improve reset driver Signed-off-by: Olof Johansson <olof@lixom.net>
2 parents 56acb3e + d0c2d21 commit 4656121

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‎Documentation/devicetree/bindings/reset/socfpga-reset.txt

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
11
Altera SOCFPGA Reset Manager
22

33
Required properties:
4-
- compatible : "altr,rst-mgr"
4+
- compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10)
5+
"altr,stratix10-rst-mgr","altr,rst-mgr" for Stratix10 ARM64 SoC
56
- reg : Should contain 1 register ranges(address and length)
67
- altr,modrst-offset : Should contain the offset of the first modrst register.
78
- #reset-cells: 1

‎Documentation/devicetree/bindings/reset/uniphier-reset.txt

Lines changed: 14 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -120,27 +120,30 @@ Example:
120120
};
121121

122122

123-
USB3 core reset
124-
---------------
123+
Peripheral core reset in glue layer
124+
-----------------------------------
125125

126-
USB3 core reset belongs to USB3 glue layer. Before using the core reset,
127-
it is necessary to control the clocks and resets to enable this layer.
128-
These clocks and resets should be described in each property.
126+
Some peripheral core reset belongs to its own glue layer. Before using
127+
this core reset, it is necessary to control the clocks and resets to enable
128+
this layer. These clocks and resets should be described in each property.
129129

130130
Required properties:
131131
- compatible: Should be
132-
"socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC
133-
"socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC
134-
"socionext,uniphier-ld20-usb3-reset" - for LD20 SoC
135-
"socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC
132+
"socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
133+
"socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
134+
"socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
135+
"socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
136+
"socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI
137+
"socionext,uniphier-pxs2-ahci-reset" - for PXs2 SoC AHCI
138+
"socionext,uniphier-pxs3-ahci-reset" - for PXs3 SoC AHCI
136139
- #reset-cells: Should be 1.
137140
- reg: Specifies offset and length of the register set for the device.
138-
- clocks: A list of phandles to the clock gate for USB3 glue layer.
141+
- clocks: A list of phandles to the clock gate for the glue layer.
139142
According to the clock-names, appropriate clocks are required.
140143
- clock-names: Should contain
141144
"gio", "link" - for Pro4 SoC
142145
"link" - for others
143-
- resets: A list of phandles to the reset control for USB3 glue layer.
146+
- resets: A list of phandles to the reset control for the glue layer.
144147
According to the reset-names, appropriate resets are required.
145148
- reset-names: Should contain
146149
"gio", "link" - for Pro4 SoC

‎arch/arm/mach-socfpga/socfpga.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,8 @@ void __iomem *rst_manager_base_addr;
3232
void __iomem *sdr_ctl_base_addr;
3333
unsigned long socfpga_cpu1start_addr;
3434

35+
extern void __init socfpga_reset_init(void);
36+
3537
static void __init socfpga_sysmgr_init(void)
3638
{
3739
struct device_node *np;
@@ -64,6 +66,7 @@ static void __init socfpga_init_irq(void)
6466

6567
if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
6668
socfpga_init_ocram_ecc();
69+
socfpga_reset_init();
6770
}
6871

6972
static void __init socfpga_arria10_init_irq(void)
@@ -74,6 +77,7 @@ static void __init socfpga_arria10_init_irq(void)
7477
socfpga_init_arria10_l2_ecc();
7578
if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
7679
socfpga_init_arria10_ocram_ecc();
80+
socfpga_reset_init();
7781
}
7882

7983
static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)

‎drivers/reset/Kconfig

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -109,7 +109,7 @@ config RESET_QCOM_PDC
109109

110110
config RESET_SIMPLE
111111
bool "Simple Reset Controller Driver" if COMPILE_TEST
112-
default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
112+
default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
113113
help
114114
This enables a simple reset controller driver for reset lines that
115115
that can be asserted and deasserted by toggling bits in a contiguous,
@@ -128,6 +128,14 @@ config RESET_STM32MP157
128128
help
129129
This enables the RCC reset controller driver for STM32 MPUs.
130130

131+
config RESET_SOCFPGA
132+
bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
133+
default ARCH_SOCFPGA
134+
select RESET_SIMPLE
135+
help
136+
This enables the reset driver for the SoCFPGA ARMv7 platforms. This
137+
driver gets initialized early during platform init calls.
138+
131139
config RESET_SUNXI
132140
bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
133141
default ARCH_SUNXI
@@ -163,15 +171,15 @@ config RESET_UNIPHIER
163171
Say Y if you want to control reset signals provided by System Control
164172
block, Media I/O block, Peripheral Block.
165173

166-
config RESET_UNIPHIER_USB3
167-
tristate "USB3 reset driver for UniPhier SoCs"
174+
config RESET_UNIPHIER_GLUE
175+
tristate "Reset driver in glue layer for UniPhier SoCs"
168176
depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
169177
default ARCH_UNIPHIER
170178
select RESET_SIMPLE
171179
help
172-
Support for the USB3 core reset on UniPhier SoCs.
173-
Say Y if you want to control reset signals provided by
174-
USB3 glue layer.
180+
Support for peripheral core reset included in its own glue layer
181+
on UniPhier SoCs. Say Y if you want to control reset signals
182+
provided by the glue layer.
175183

176184
config RESET_ZYNQ
177185
bool "ZYNQ Reset Driver" if COMPILE_TEST

‎drivers/reset/Makefile

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,10 +19,11 @@ obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
1919
obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
2020
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
2121
obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
22+
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
2223
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
2324
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
2425
obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
2526
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
26-
obj-$(CONFIG_RESET_UNIPHIER_USB3) += reset-uniphier-usb3.o
27+
obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o
2728
obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
2829

‎drivers/reset/core.c

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -795,3 +795,45 @@ devm_reset_control_array_get(struct device *dev, bool shared, bool optional)
795795
return rstc;
796796
}
797797
EXPORT_SYMBOL_GPL(devm_reset_control_array_get);
798+
799+
static int reset_control_get_count_from_lookup(struct device *dev)
800+
{
801+
const struct reset_control_lookup *lookup;
802+
const char *dev_id;
803+
int count = 0;
804+
805+
if (!dev)
806+
return -EINVAL;
807+
808+
dev_id = dev_name(dev);
809+
mutex_lock(&reset_lookup_mutex);
810+
811+
list_for_each_entry(lookup, &reset_lookup_list, list) {
812+
if (!strcmp(lookup->dev_id, dev_id))
813+
count++;
814+
}
815+
816+
mutex_unlock(&reset_lookup_mutex);
817+
818+
if (count == 0)
819+
count = -ENOENT;
820+
821+
return count;
822+
}
823+
824+
/**
825+
* reset_control_get_count - Count number of resets available with a device
826+
*
827+
* @dev: device for which to return the number of resets
828+
*
829+
* Returns positive reset count on success, or error number on failure and
830+
* on count being zero.
831+
*/
832+
int reset_control_get_count(struct device *dev)
833+
{
834+
if (dev->of_node)
835+
return of_reset_control_get_count(dev->of_node);
836+
837+
return reset_control_get_count_from_lookup(dev);
838+
}
839+
EXPORT_SYMBOL_GPL(reset_control_get_count);

‎drivers/reset/reset-hsdk.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -86,6 +86,7 @@ static int hsdk_reset_reset(struct reset_controller_dev *rcdev,
8686

8787
static const struct reset_control_ops hsdk_reset_ops = {
8888
.reset = hsdk_reset_reset,
89+
.deassert = hsdk_reset_reset,
8990
};
9091

9192
static int hsdk_reset_probe(struct platform_device *pdev)

‎drivers/reset/reset-simple.c

Lines changed: 3 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -109,7 +109,7 @@ struct reset_simple_devdata {
109109
#define SOCFPGA_NR_BANKS 8
110110

111111
static const struct reset_simple_devdata reset_simple_socfpga = {
112-
.reg_offset = 0x10,
112+
.reg_offset = 0x20,
113113
.nr_resets = SOCFPGA_NR_BANKS * 32,
114114
.status_active_low = true,
115115
};
@@ -120,7 +120,8 @@ static const struct reset_simple_devdata reset_simple_active_low = {
120120
};
121121

122122
static const struct of_device_id reset_simple_dt_ids[] = {
123-
{ .compatible = "altr,rst-mgr", .data = &reset_simple_socfpga },
123+
{ .compatible = "altr,stratix10-rst-mgr",
124+
.data = &reset_simple_socfpga },
124125
{ .compatible = "st,stm32-rcc", },
125126
{ .compatible = "allwinner,sun6i-a31-clock-reset",
126127
.data = &reset_simple_active_low },
@@ -166,14 +167,6 @@ static int reset_simple_probe(struct platform_device *pdev)
166167
data->status_active_low = devdata->status_active_low;
167168
}
168169

169-
if (of_device_is_compatible(dev->of_node, "altr,rst-mgr") &&
170-
of_property_read_u32(dev->of_node, "altr,modrst-offset",
171-
&reg_offset)) {
172-
dev_warn(dev,
173-
"missing altr,modrst-offset property, assuming 0x%x!\n",
174-
reg_offset);
175-
}
176-
177170
data->membase += reg_offset;
178171

179172
return devm_reset_controller_register(dev, &data->rcdev);

‎drivers/reset/reset-socfpga.c

Lines changed: 88 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,88 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* Copyright (C) 2018, Intel Corporation
4+
* Copied from reset-sunxi.c
5+
*/
6+
7+
#include <linux/err.h>
8+
#include <linux/io.h>
9+
#include <linux/init.h>
10+
#include <linux/of.h>
11+
#include <linux/of_address.h>
12+
#include <linux/platform_device.h>
13+
#include <linux/reset-controller.h>
14+
#include <linux/slab.h>
15+
#include <linux/spinlock.h>
16+
#include <linux/types.h>
17+
18+
#include "reset-simple.h"
19+
20+
#define SOCFPGA_NR_BANKS 8
21+
void __init socfpga_reset_init(void);
22+
23+
static int a10_reset_init(struct device_node *np)
24+
{
25+
struct reset_simple_data *data;
26+
struct resource res;
27+
resource_size_t size;
28+
int ret;
29+
u32 reg_offset = 0x10;
30+
31+
data = kzalloc(sizeof(*data), GFP_KERNEL);
32+
if (!data)
33+
return -ENOMEM;
34+
35+
ret = of_address_to_resource(np, 0, &res);
36+
if (ret)
37+
goto err_alloc;
38+
39+
size = resource_size(&res);
40+
if (!request_mem_region(res.start, size, np->name)) {
41+
ret = -EBUSY;
42+
goto err_alloc;
43+
}
44+
45+
data->membase = ioremap(res.start, size);
46+
if (!data->membase) {
47+
ret = -ENOMEM;
48+
goto err_alloc;
49+
}
50+
51+
if (of_property_read_u32(np, "altr,modrst-offset", &reg_offset))
52+
pr_warn("missing altr,modrst-offset property, assuming 0x10\n");
53+
data->membase += reg_offset;
54+
55+
spin_lock_init(&data->lock);
56+
57+
data->rcdev.owner = THIS_MODULE;
58+
data->rcdev.nr_resets = SOCFPGA_NR_BANKS * 32;
59+
data->rcdev.ops = &reset_simple_ops;
60+
data->rcdev.of_node = np;
61+
data->status_active_low = true;
62+
63+
return reset_controller_register(&data->rcdev);
64+
65+
err_alloc:
66+
kfree(data);
67+
return ret;
68+
};
69+
70+
/*
71+
* These are the reset controller we need to initialize early on in
72+
* our system, before we can even think of using a regular device
73+
* driver for it.
74+
* The controllers that we can register through the regular device
75+
* model are handled by the simple reset driver directly.
76+
*/
77+
static const struct of_device_id socfpga_early_reset_dt_ids[] __initconst = {
78+
{ .compatible = "altr,rst-mgr", },
79+
{ /* sentinel */ },
80+
};
81+
82+
void __init socfpga_reset_init(void)
83+
{
84+
struct device_node *np;
85+
86+
for_each_matching_node(np, socfpga_early_reset_dt_ids)
87+
a10_reset_init(np);
88+
}

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