NXP i.MX Messaging Unit (MU)

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The Messaging Unit module enables two processors within the SoC to

communicate and coordinate by passing messages (e.g. data, status

and control) through the MU interface. The MU also provides the ability

for one processor to signal the other processor using interrupts.

Because the MU manages the messaging between processors, the MU uses

different clocks (from each side of the different peripheral buses).

Therefore, the MU must synchronize the accesses from one side to the

other. The MU accomplishes synchronization using two sets of matching

registers (Processor A-facing, Processor B-facing).

Messaging Unit Device Node:

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Required properties:

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- compatible : should be "fsl,<chip>-mu", the supported chips include

imx8qxp, imx8qm.

- reg : Should contain the registers location and length

- interrupts : Interrupt number. The interrupt specifier format depends

on the interrupt controller parent.

- #mbox-cells: Must be 0. Number of cells in a mailbox

Examples:

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lsio_mu0: mailbox@5d1b0000 {

compatible = "fsl,imx8qxp-mu";

reg = <0x0 0x5d1b0000 0x0 0x10000>;

interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;

#mbox-cells = <0>;

};