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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd: "Mostly driver fixes, but there's a core framework fix in here too: - Revert the commits that introduce clk management for the SP clk on MMP2 SoCs (used for OLPC). Turns out it wasn't a good idea and there isn't any need to manage this clk, it just causes more headaches. - A performance regression that went unnoticed for many years where we would traverse the entire clk tree looking for a clk by name when we already have the pointer to said clk that we're looking for - A parent linkage fix for the qcom SDM845 clk driver - An i.MX clk driver rate miscalculation fix where order of operations were messed up - One error handling fix from the static checkers" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: qcom: gcc: Use active only source for CPUSS clocks clk: ti: Fix error handling in ti_clk_parse_divider_data() clk: imx: Fix fractional clock set rate computation clk: Remove global clk traversal on fetch parent index Revert "dt-bindings: marvell,mmp2: Add clock id for the SP clock" Revert "clk: mmp2: add SP clock" Revert "Input: olpc_apsp - enable the SP clock"
2 parents 52107c5 + 9ff1a3b commit 5b4746a

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+35
-32
lines changed

8 files changed

+35
-32
lines changed

Documentation/devicetree/bindings/serio/olpc,ap-sp.txt

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,14 +4,10 @@ Required properties:
44
- compatible : "olpc,ap-sp"
55
- reg : base address and length of SoC's WTM registers
66
- interrupts : SP-AP interrupt
7-
- clocks : phandle + clock-specifier for the clock that drives the WTM
8-
- clock-names: should be "sp"
97

108
Example:
119
ap-sp@d4290000 {
1210
compatible = "olpc,ap-sp";
1311
reg = <0xd4290000 0x1000>;
1412
interrupts = <40>;
15-
clocks = <&soc_clocks MMP2_CLK_SP>;
16-
clock-names = "sp";
1713
}

drivers/clk/clk.c

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1513,9 +1513,19 @@ static int clk_fetch_parent_index(struct clk_core *core,
15131513
if (!parent)
15141514
return -EINVAL;
15151515

1516-
for (i = 0; i < core->num_parents; i++)
1517-
if (clk_core_get_parent_by_index(core, i) == parent)
1516+
for (i = 0; i < core->num_parents; i++) {
1517+
if (core->parents[i] == parent)
1518+
return i;
1519+
1520+
if (core->parents[i])
1521+
continue;
1522+
1523+
/* Fallback to comparing globally unique names */
1524+
if (!strcmp(parent->name, core->parent_names[i])) {
1525+
core->parents[i] = parent;
15181526
return i;
1527+
}
1528+
}
15191529

15201530
return -EINVAL;
15211531
}

drivers/clk/imx/clk-frac-pll.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -155,13 +155,14 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
155155
{
156156
struct clk_frac_pll *pll = to_clk_frac_pll(hw);
157157
u32 val, divfi, divff;
158-
u64 temp64 = parent_rate;
158+
u64 temp64;
159159
int ret;
160160

161161
parent_rate *= 8;
162162
rate *= 2;
163163
divfi = rate / parent_rate;
164-
temp64 *= rate - divfi;
164+
temp64 = parent_rate * divfi;
165+
temp64 = rate - temp64;
165166
temp64 *= PLL_FRAC_DENOM;
166167
do_div(temp64, parent_rate);
167168
divff = temp64;

drivers/clk/mmp/clk-of-mmp2.c

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,6 @@
5353
#define APMU_DISP1 0x110
5454
#define APMU_CCIC0 0x50
5555
#define APMU_CCIC1 0xf4
56-
#define APMU_SP 0x68
5756
#define MPMU_UART_PLL 0x14
5857

5958
struct mmp2_clk_unit {
@@ -210,8 +209,6 @@ static struct mmp_clk_mix_config ccic1_mix_config = {
210209
.reg_info = DEFINE_MIX_REG_INFO(4, 16, 2, 6, 32),
211210
};
212211

213-
static DEFINE_SPINLOCK(sp_lock);
214-
215212
static struct mmp_param_mux_clk apmu_mux_clks[] = {
216213
{MMP2_CLK_DISP0_MUX, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 2, 0, &disp0_lock},
217214
{MMP2_CLK_DISP1_MUX, "disp1_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP1, 6, 2, 0, &disp1_lock},
@@ -242,7 +239,6 @@ static struct mmp_param_gate_clk apmu_gate_clks[] = {
242239
{MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock},
243240
{MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock},
244241
{MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock},
245-
{MMP2_CLK_SP, "sp_clk", NULL, CLK_SET_RATE_PARENT, APMU_SP, 0x1b, 0x1b, 0x0, 0, &sp_lock},
246242
};
247243

248244
static void mmp2_axi_periph_clk_init(struct mmp2_clk_unit *pxa_unit)

drivers/clk/qcom/gcc-sdm845.c

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -115,8 +115,8 @@ static const char * const gcc_parent_names_6[] = {
115115
"core_bi_pll_test_se",
116116
};
117117

118-
static const char * const gcc_parent_names_7[] = {
119-
"bi_tcxo",
118+
static const char * const gcc_parent_names_7_ao[] = {
119+
"bi_tcxo_ao",
120120
"gpll0",
121121
"gpll0_out_even",
122122
"core_bi_pll_test_se",
@@ -128,6 +128,12 @@ static const char * const gcc_parent_names_8[] = {
128128
"core_bi_pll_test_se",
129129
};
130130

131+
static const char * const gcc_parent_names_8_ao[] = {
132+
"bi_tcxo_ao",
133+
"gpll0",
134+
"core_bi_pll_test_se",
135+
};
136+
131137
static const struct parent_map gcc_parent_map_10[] = {
132138
{ P_BI_TCXO, 0 },
133139
{ P_GPLL0_OUT_MAIN, 1 },
@@ -210,7 +216,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
210216
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
211217
.clkr.hw.init = &(struct clk_init_data){
212218
.name = "gcc_cpuss_ahb_clk_src",
213-
.parent_names = gcc_parent_names_7,
219+
.parent_names = gcc_parent_names_7_ao,
214220
.num_parents = 4,
215221
.ops = &clk_rcg2_ops,
216222
},
@@ -229,7 +235,7 @@ static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
229235
.freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
230236
.clkr.hw.init = &(struct clk_init_data){
231237
.name = "gcc_cpuss_rbcpr_clk_src",
232-
.parent_names = gcc_parent_names_8,
238+
.parent_names = gcc_parent_names_8_ao,
233239
.num_parents = 3,
234240
.ops = &clk_rcg2_ops,
235241
},

drivers/clk/ti/divider.c

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -403,8 +403,10 @@ int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
403403
num_dividers = i;
404404

405405
tmp = kcalloc(valid_div + 1, sizeof(*tmp), GFP_KERNEL);
406-
if (!tmp)
406+
if (!tmp) {
407+
*table = ERR_PTR(-ENOMEM);
407408
return -ENOMEM;
409+
}
408410

409411
valid_div = 0;
410412
*width = 0;
@@ -439,6 +441,7 @@ struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup)
439441
{
440442
struct clk_omap_divider *div;
441443
struct clk_omap_reg *reg;
444+
int ret;
442445

443446
if (!setup)
444447
return NULL;
@@ -458,6 +461,12 @@ struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup)
458461
div->flags |= CLK_DIVIDER_POWER_OF_TWO;
459462

460463
div->table = _get_div_table_from_setup(setup, &div->width);
464+
if (IS_ERR(div->table)) {
465+
ret = PTR_ERR(div->table);
466+
kfree(div);
467+
return ERR_PTR(ret);
468+
}
469+
461470

462471
div->shift = setup->bit_shift;
463472
div->latch = -EINVAL;

drivers/input/serio/olpc_apsp.c

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,6 @@
2323
#include <linux/of.h>
2424
#include <linux/slab.h>
2525
#include <linux/delay.h>
26-
#include <linux/clk.h>
2726

2827
/*
2928
* The OLPC XO-1.75 and XO-4 laptops do not have a hardware PS/2 controller.
@@ -75,7 +74,6 @@ struct olpc_apsp {
7574
struct serio *kbio;
7675
struct serio *padio;
7776
void __iomem *base;
78-
struct clk *clk;
7977
int open_count;
8078
int irq;
8179
};
@@ -148,17 +146,11 @@ static int olpc_apsp_open(struct serio *port)
148146
struct olpc_apsp *priv = port->port_data;
149147
unsigned int tmp;
150148
unsigned long l;
151-
int error;
152149

153150
if (priv->open_count++ == 0) {
154-
error = clk_prepare_enable(priv->clk);
155-
if (error)
156-
return error;
157-
158151
l = readl(priv->base + COMMAND_FIFO_STATUS);
159152
if (!(l & CMD_STS_MASK)) {
160153
dev_err(priv->dev, "SP cannot accept commands.\n");
161-
clk_disable_unprepare(priv->clk);
162154
return -EIO;
163155
}
164156

@@ -179,8 +171,6 @@ static void olpc_apsp_close(struct serio *port)
179171
/* Disable interrupt 0 */
180172
tmp = readl(priv->base + PJ_INTERRUPT_MASK);
181173
writel(tmp | INT_0, priv->base + PJ_INTERRUPT_MASK);
182-
183-
clk_disable_unprepare(priv->clk);
184174
}
185175
}
186176

@@ -208,10 +198,6 @@ static int olpc_apsp_probe(struct platform_device *pdev)
208198
if (priv->irq < 0)
209199
return priv->irq;
210200

211-
priv->clk = devm_clk_get(&pdev->dev, "sp");
212-
if (IS_ERR(priv->clk))
213-
return PTR_ERR(priv->clk);
214-
215201
/* KEYBOARD */
216202
kb_serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
217203
if (!kb_serio)

include/dt-bindings/clock/marvell,mmp2.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,6 @@
7171
#define MMP2_CLK_CCIC1_MIX 117
7272
#define MMP2_CLK_CCIC1_PHY 118
7373
#define MMP2_CLK_CCIC1_SPHY 119
74-
#define MMP2_CLK_SP 120
7574

7675
#define MMP2_NR_CLKS 200
7776
#endif

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