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airliedairlied
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Merge tag 'drm-intel-fixes-2018-11-08' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
Bugzilla #108282 fixed: Avoid graphics corruption on 32-bit systems for Mesa 18.2.x Avoid OOPS on LPE audio deinit. Remove two unused W/As. Fix to correct HDMI 2.0 audio clock modes to spec. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181108134508.GA28466@jlahtine-desk.ger.corp.intel.com
2 parents d08f44b + 214782d commit 7d588f9

17 files changed

+145
-135
lines changed

‎drivers/gpu/drm/i915/gvt/gtt.c

Lines changed: 58 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -1905,7 +1905,6 @@ static struct intel_vgpu_mm *intel_vgpu_create_ggtt_mm(struct intel_vgpu *vgpu)
19051905
vgpu_free_mm(mm);
19061906
return ERR_PTR(-ENOMEM);
19071907
}
1908-
mm->ggtt_mm.last_partial_off = -1UL;
19091908

19101909
return mm;
19111910
}
@@ -1930,7 +1929,6 @@ void _intel_vgpu_mm_release(struct kref *mm_ref)
19301929
invalidate_ppgtt_mm(mm);
19311930
} else {
19321931
vfree(mm->ggtt_mm.virtual_ggtt);
1933-
mm->ggtt_mm.last_partial_off = -1UL;
19341932
}
19351933

19361934
vgpu_free_mm(mm);
@@ -2168,6 +2166,8 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
21682166
struct intel_gvt_gtt_entry e, m;
21692167
dma_addr_t dma_addr;
21702168
int ret;
2169+
struct intel_gvt_partial_pte *partial_pte, *pos, *n;
2170+
bool partial_update = false;
21712171

21722172
if (bytes != 4 && bytes != 8)
21732173
return -EINVAL;
@@ -2178,68 +2178,57 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
21782178
if (!vgpu_gmadr_is_valid(vgpu, gma))
21792179
return 0;
21802180

2181-
ggtt_get_guest_entry(ggtt_mm, &e, g_gtt_index);
2182-
2181+
e.type = GTT_TYPE_GGTT_PTE;
21832182
memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data,
21842183
bytes);
21852184

21862185
/* If ggtt entry size is 8 bytes, and it's split into two 4 bytes
2187-
* write, we assume the two 4 bytes writes are consecutive.
2188-
* Otherwise, we abort and report error
2186+
* write, save the first 4 bytes in a list and update virtual
2187+
* PTE. Only update shadow PTE when the second 4 bytes comes.
21892188
*/
21902189
if (bytes < info->gtt_entry_size) {
2191-
if (ggtt_mm->ggtt_mm.last_partial_off == -1UL) {
2192-
/* the first partial part*/
2193-
ggtt_mm->ggtt_mm.last_partial_off = off;
2194-
ggtt_mm->ggtt_mm.last_partial_data = e.val64;
2195-
return 0;
2196-
} else if ((g_gtt_index ==
2197-
(ggtt_mm->ggtt_mm.last_partial_off >>
2198-
info->gtt_entry_size_shift)) &&
2199-
(off != ggtt_mm->ggtt_mm.last_partial_off)) {
2200-
/* the second partial part */
2201-
2202-
int last_off = ggtt_mm->ggtt_mm.last_partial_off &
2203-
(info->gtt_entry_size - 1);
2204-
2205-
memcpy((void *)&e.val64 + last_off,
2206-
(void *)&ggtt_mm->ggtt_mm.last_partial_data +
2207-
last_off, bytes);
2208-
2209-
ggtt_mm->ggtt_mm.last_partial_off = -1UL;
2210-
} else {
2211-
int last_offset;
2212-
2213-
gvt_vgpu_err("failed to populate guest ggtt entry: abnormal ggtt entry write sequence, last_partial_off=%lx, offset=%x, bytes=%d, ggtt entry size=%d\n",
2214-
ggtt_mm->ggtt_mm.last_partial_off, off,
2215-
bytes, info->gtt_entry_size);
2216-
2217-
/* set host ggtt entry to scratch page and clear
2218-
* virtual ggtt entry as not present for last
2219-
* partially write offset
2220-
*/
2221-
last_offset = ggtt_mm->ggtt_mm.last_partial_off &
2222-
(~(info->gtt_entry_size - 1));
2223-
2224-
ggtt_get_host_entry(ggtt_mm, &m, last_offset);
2225-
ggtt_invalidate_pte(vgpu, &m);
2226-
ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2227-
ops->clear_present(&m);
2228-
ggtt_set_host_entry(ggtt_mm, &m, last_offset);
2229-
ggtt_invalidate(gvt->dev_priv);
2230-
2231-
ggtt_get_guest_entry(ggtt_mm, &e, last_offset);
2232-
ops->clear_present(&e);
2233-
ggtt_set_guest_entry(ggtt_mm, &e, last_offset);
2234-
2235-
ggtt_mm->ggtt_mm.last_partial_off = off;
2236-
ggtt_mm->ggtt_mm.last_partial_data = e.val64;
2190+
bool found = false;
2191+
2192+
list_for_each_entry_safe(pos, n,
2193+
&ggtt_mm->ggtt_mm.partial_pte_list, list) {
2194+
if (g_gtt_index == pos->offset >>
2195+
info->gtt_entry_size_shift) {
2196+
if (off != pos->offset) {
2197+
/* the second partial part*/
2198+
int last_off = pos->offset &
2199+
(info->gtt_entry_size - 1);
2200+
2201+
memcpy((void *)&e.val64 + last_off,
2202+
(void *)&pos->data + last_off,
2203+
bytes);
2204+
2205+
list_del(&pos->list);
2206+
kfree(pos);
2207+
found = true;
2208+
break;
2209+
}
2210+
2211+
/* update of the first partial part */
2212+
pos->data = e.val64;
2213+
ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2214+
return 0;
2215+
}
2216+
}
22372217

2238-
return 0;
2218+
if (!found) {
2219+
/* the first partial part */
2220+
partial_pte = kzalloc(sizeof(*partial_pte), GFP_KERNEL);
2221+
if (!partial_pte)
2222+
return -ENOMEM;
2223+
partial_pte->offset = off;
2224+
partial_pte->data = e.val64;
2225+
list_add_tail(&partial_pte->list,
2226+
&ggtt_mm->ggtt_mm.partial_pte_list);
2227+
partial_update = true;
22392228
}
22402229
}
22412230

2242-
if (ops->test_present(&e)) {
2231+
if (!partial_update && (ops->test_present(&e))) {
22432232
gfn = ops->get_pfn(&e);
22442233
m = e;
22452234

@@ -2263,16 +2252,18 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
22632252
} else
22642253
ops->set_pfn(&m, dma_addr >> PAGE_SHIFT);
22652254
} else {
2266-
ggtt_get_host_entry(ggtt_mm, &m, g_gtt_index);
2267-
ggtt_invalidate_pte(vgpu, &m);
22682255
ops->set_pfn(&m, gvt->gtt.scratch_mfn);
22692256
ops->clear_present(&m);
22702257
}
22712258

22722259
out:
2260+
ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2261+
2262+
ggtt_get_host_entry(ggtt_mm, &e, g_gtt_index);
2263+
ggtt_invalidate_pte(vgpu, &e);
2264+
22732265
ggtt_set_host_entry(ggtt_mm, &m, g_gtt_index);
22742266
ggtt_invalidate(gvt->dev_priv);
2275-
ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
22762267
return 0;
22772268
}
22782269

@@ -2430,6 +2421,8 @@ int intel_vgpu_init_gtt(struct intel_vgpu *vgpu)
24302421

24312422
intel_vgpu_reset_ggtt(vgpu, false);
24322423

2424+
INIT_LIST_HEAD(&gtt->ggtt_mm->ggtt_mm.partial_pte_list);
2425+
24332426
return create_scratch_page_tree(vgpu);
24342427
}
24352428

@@ -2454,6 +2447,14 @@ static void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu)
24542447

24552448
static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu)
24562449
{
2450+
struct intel_gvt_partial_pte *pos;
2451+
2452+
list_for_each_entry(pos,
2453+
&vgpu->gtt.ggtt_mm->ggtt_mm.partial_pte_list, list) {
2454+
gvt_dbg_mm("partial PTE update on hold 0x%lx : 0x%llx\n",
2455+
pos->offset, pos->data);
2456+
kfree(pos);
2457+
}
24572458
intel_vgpu_destroy_mm(vgpu->gtt.ggtt_mm);
24582459
vgpu->gtt.ggtt_mm = NULL;
24592460
}

‎drivers/gpu/drm/i915/gvt/gtt.h

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,6 @@
3535
#define _GVT_GTT_H_
3636

3737
#define I915_GTT_PAGE_SHIFT 12
38-
#define I915_GTT_PAGE_MASK (~(I915_GTT_PAGE_SIZE - 1))
3938

4039
struct intel_vgpu_mm;
4140

@@ -133,6 +132,12 @@ enum intel_gvt_mm_type {
133132

134133
#define GVT_RING_CTX_NR_PDPS GEN8_3LVL_PDPES
135134

135+
struct intel_gvt_partial_pte {
136+
unsigned long offset;
137+
u64 data;
138+
struct list_head list;
139+
};
140+
136141
struct intel_vgpu_mm {
137142
enum intel_gvt_mm_type type;
138143
struct intel_vgpu *vgpu;
@@ -157,8 +162,7 @@ struct intel_vgpu_mm {
157162
} ppgtt_mm;
158163
struct {
159164
void *virtual_ggtt;
160-
unsigned long last_partial_off;
161-
u64 last_partial_data;
165+
struct list_head partial_pte_list;
162166
} ggtt_mm;
163167
};
164168
};

‎drivers/gpu/drm/i915/gvt/handlers.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1609,7 +1609,7 @@ static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu,
16091609
return 0;
16101610
}
16111611

1612-
static int bxt_edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
1612+
static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
16131613
unsigned int offset, void *p_data, unsigned int bytes)
16141614
{
16151615
vgpu_vreg(vgpu, offset) = 0;
@@ -2607,6 +2607,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
26072607
MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
26082608
MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
26092609
MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2610+
2611+
MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2612+
MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
26102613
return 0;
26112614
}
26122615

@@ -3205,9 +3208,6 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
32053208
MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
32063209
MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
32073210

3208-
MMIO_DH(EDP_PSR_IMR, D_BXT, NULL, bxt_edp_psr_imr_iir_write);
3209-
MMIO_DH(EDP_PSR_IIR, D_BXT, NULL, bxt_edp_psr_imr_iir_write);
3210-
32113211
MMIO_D(RC6_CTX_BASE, D_BXT);
32123212

32133213
MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);

‎drivers/gpu/drm/i915/gvt/mmio_context.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
131131
{RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
132132

133133
{RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
134-
{RCS, GEN9_CSFE_CHICKEN1_RCS, 0x0, false}, /* 0x20d4 */
134+
{RCS, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
135135

136136
{RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
137137
{RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */

‎drivers/gpu/drm/i915/i915_drv.c

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1175,8 +1175,6 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
11751175
return -EINVAL;
11761176
}
11771177

1178-
dram_info->valid_dimm = true;
1179-
11801178
/*
11811179
* If any of the channel is single rank channel, worst case output
11821180
* will be same as if single rank memory, so consider single rank
@@ -1193,8 +1191,7 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
11931191
return -EINVAL;
11941192
}
11951193

1196-
if (ch0.is_16gb_dimm || ch1.is_16gb_dimm)
1197-
dram_info->is_16gb_dimm = true;
1194+
dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
11981195

11991196
dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,
12001197
val_ch1,
@@ -1314,7 +1311,6 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
13141311
return -EINVAL;
13151312
}
13161313

1317-
dram_info->valid_dimm = true;
13181314
dram_info->valid = true;
13191315
return 0;
13201316
}
@@ -1327,12 +1323,17 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
13271323
int ret;
13281324

13291325
dram_info->valid = false;
1330-
dram_info->valid_dimm = false;
1331-
dram_info->is_16gb_dimm = false;
13321326
dram_info->rank = I915_DRAM_RANK_INVALID;
13331327
dram_info->bandwidth_kbps = 0;
13341328
dram_info->num_channels = 0;
13351329

1330+
/*
1331+
* Assume 16Gb DIMMs are present until proven otherwise.
1332+
* This is only used for the level 0 watermark latency
1333+
* w/a which does not apply to bxt/glk.
1334+
*/
1335+
dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1336+
13361337
if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))
13371338
return;
13381339

‎drivers/gpu/drm/i915/i915_drv.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1948,7 +1948,6 @@ struct drm_i915_private {
19481948

19491949
struct dram_info {
19501950
bool valid;
1951-
bool valid_dimm;
19521951
bool is_16gb_dimm;
19531952
u8 num_channels;
19541953
enum dram_rank {

‎drivers/gpu/drm/i915/i915_gem_execbuffer.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -460,7 +460,7 @@ eb_validate_vma(struct i915_execbuffer *eb,
460460
* any non-page-aligned or non-canonical addresses.
461461
*/
462462
if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
463-
entry->offset != gen8_canonical_addr(entry->offset & PAGE_MASK)))
463+
entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
464464
return -EINVAL;
465465

466466
/* pad_to_size was once a reserved field, so sanitize it */

‎drivers/gpu/drm/i915/i915_gem_gtt.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1757,7 +1757,7 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base, struct seq_file *m)
17571757
if (i == 4)
17581758
continue;
17591759

1760-
seq_printf(m, "\t\t(%03d, %04d) %08lx: ",
1760+
seq_printf(m, "\t\t(%03d, %04d) %08llx: ",
17611761
pde, pte,
17621762
(pde * GEN6_PTES + pte) * I915_GTT_PAGE_SIZE);
17631763
for (i = 0; i < 4; i++) {

‎drivers/gpu/drm/i915/i915_gem_gtt.h

Lines changed: 19 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -42,13 +42,15 @@
4242
#include "i915_selftest.h"
4343
#include "i915_timeline.h"
4444

45-
#define I915_GTT_PAGE_SIZE_4K BIT(12)
46-
#define I915_GTT_PAGE_SIZE_64K BIT(16)
47-
#define I915_GTT_PAGE_SIZE_2M BIT(21)
45+
#define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
46+
#define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
47+
#define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
4848

4949
#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
5050
#define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
5151

52+
#define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
53+
5254
#define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
5355

5456
#define I915_FENCE_REG_NONE -1
@@ -659,20 +661,20 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
659661
u64 start, u64 end, unsigned int flags);
660662

661663
/* Flags used by pin/bind&friends. */
662-
#define PIN_NONBLOCK BIT(0)
663-
#define PIN_MAPPABLE BIT(1)
664-
#define PIN_ZONE_4G BIT(2)
665-
#define PIN_NONFAULT BIT(3)
666-
#define PIN_NOEVICT BIT(4)
667-
668-
#define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */
669-
#define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */
670-
#define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */
671-
#define PIN_UPDATE BIT(8)
672-
673-
#define PIN_HIGH BIT(9)
674-
#define PIN_OFFSET_BIAS BIT(10)
675-
#define PIN_OFFSET_FIXED BIT(11)
664+
#define PIN_NONBLOCK BIT_ULL(0)
665+
#define PIN_MAPPABLE BIT_ULL(1)
666+
#define PIN_ZONE_4G BIT_ULL(2)
667+
#define PIN_NONFAULT BIT_ULL(3)
668+
#define PIN_NOEVICT BIT_ULL(4)
669+
670+
#define PIN_MBZ BIT_ULL(5) /* I915_VMA_PIN_OVERFLOW */
671+
#define PIN_GLOBAL BIT_ULL(6) /* I915_VMA_GLOBAL_BIND */
672+
#define PIN_USER BIT_ULL(7) /* I915_VMA_LOCAL_BIND */
673+
#define PIN_UPDATE BIT_ULL(8)
674+
675+
#define PIN_HIGH BIT_ULL(9)
676+
#define PIN_OFFSET_BIAS BIT_ULL(10)
677+
#define PIN_OFFSET_FIXED BIT_ULL(11)
676678
#define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE)
677679

678680
#endif

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