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drm/i915/icl: combo port vswing programming changes per BSPEC
In August 2018 the BSPEC changed the ICL port programming sequence to closely resemble earlier gen programming sequence. Restrict combo phy to HBR max rate unless eDP panel is connected to port. v2: remove debug code that Imre found v3: simplify translation table if-else v4: edp translation table now based on link rate and low_swing v5: Misc review comments + r-b BSpec: 21257 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1545084827-5776-1-git-send-email-clinton.a.taylor@intel.com (cherry picked from commit b265a2a) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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-153
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3 files changed

+93
-153
lines changed

‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1866,6 +1866,10 @@ enum i915_power_well_id {
18661866

18671867
#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
18681868
#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
1869+
#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
1870+
#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
1871+
#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
1872+
#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
18691873
#define N_SCALAR(x) ((x) << 24)
18701874
#define N_SCALAR_MASK (0x7F << 24)
18711875

‎drivers/gpu/drm/i915/intel_ddi.c

Lines changed: 86 additions & 152 deletions
Original file line numberDiff line numberDiff line change
@@ -494,103 +494,58 @@ static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
494494
{ 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
495495
};
496496

497-
struct icl_combo_phy_ddi_buf_trans {
498-
u32 dw2_swing_select;
499-
u32 dw2_swing_scalar;
500-
u32 dw4_scaling;
501-
};
502-
503-
/* Voltage Swing Programming for VccIO 0.85V for DP */
504-
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
505-
/* Voltage mV db */
506-
{ 0x2, 0x98, 0x0018 }, /* 400 0.0 */
507-
{ 0x2, 0x98, 0x3015 }, /* 400 3.5 */
508-
{ 0x2, 0x98, 0x6012 }, /* 400 6.0 */
509-
{ 0x2, 0x98, 0x900F }, /* 400 9.5 */
510-
{ 0xB, 0x70, 0x0018 }, /* 600 0.0 */
511-
{ 0xB, 0x70, 0x3015 }, /* 600 3.5 */
512-
{ 0xB, 0x70, 0x6012 }, /* 600 6.0 */
513-
{ 0x5, 0x00, 0x0018 }, /* 800 0.0 */
514-
{ 0x5, 0x00, 0x3015 }, /* 800 3.5 */
515-
{ 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
516-
};
517-
518-
/* FIXME - After table is updated in Bspec */
519-
/* Voltage Swing Programming for VccIO 0.85V for eDP */
520-
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
521-
/* Voltage mV db */
522-
{ 0x0, 0x00, 0x00 }, /* 200 0.0 */
523-
{ 0x0, 0x00, 0x00 }, /* 200 1.5 */
524-
{ 0x0, 0x00, 0x00 }, /* 200 4.0 */
525-
{ 0x0, 0x00, 0x00 }, /* 200 6.0 */
526-
{ 0x0, 0x00, 0x00 }, /* 250 0.0 */
527-
{ 0x0, 0x00, 0x00 }, /* 250 1.5 */
528-
{ 0x0, 0x00, 0x00 }, /* 250 4.0 */
529-
{ 0x0, 0x00, 0x00 }, /* 300 0.0 */
530-
{ 0x0, 0x00, 0x00 }, /* 300 1.5 */
531-
{ 0x0, 0x00, 0x00 }, /* 350 0.0 */
532-
};
533-
534-
/* Voltage Swing Programming for VccIO 0.95V for DP */
535-
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
536-
/* Voltage mV db */
537-
{ 0x2, 0x98, 0x0018 }, /* 400 0.0 */
538-
{ 0x2, 0x98, 0x3015 }, /* 400 3.5 */
539-
{ 0x2, 0x98, 0x6012 }, /* 400 6.0 */
540-
{ 0x2, 0x98, 0x900F }, /* 400 9.5 */
541-
{ 0x4, 0x98, 0x0018 }, /* 600 0.0 */
542-
{ 0x4, 0x98, 0x3015 }, /* 600 3.5 */
543-
{ 0x4, 0x98, 0x6012 }, /* 600 6.0 */
544-
{ 0x5, 0x76, 0x0018 }, /* 800 0.0 */
545-
{ 0x5, 0x76, 0x3015 }, /* 800 3.5 */
546-
{ 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
497+
/* icl_combo_phy_ddi_translations */
498+
static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
499+
/* NT mV Trans mV db */
500+
{ 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
501+
{ 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
502+
{ 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
503+
{ 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
504+
{ 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
505+
{ 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
506+
{ 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
507+
{ 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
508+
{ 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
509+
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
547510
};
548511

549-
/* FIXME - After table is updated in Bspec */
550-
/* Voltage Swing Programming for VccIO 0.95V for eDP */
551-
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
552-
/* Voltage mV db */
553-
{ 0x0, 0x00, 0x00 }, /* 200 0.0 */
554-
{ 0x0, 0x00, 0x00 }, /* 200 1.5 */
555-
{ 0x0, 0x00, 0x00 }, /* 200 4.0 */
556-
{ 0x0, 0x00, 0x00 }, /* 200 6.0 */
557-
{ 0x0, 0x00, 0x00 }, /* 250 0.0 */
558-
{ 0x0, 0x00, 0x00 }, /* 250 1.5 */
559-
{ 0x0, 0x00, 0x00 }, /* 250 4.0 */
560-
{ 0x0, 0x00, 0x00 }, /* 300 0.0 */
561-
{ 0x0, 0x00, 0x00 }, /* 300 1.5 */
562-
{ 0x0, 0x00, 0x00 }, /* 350 0.0 */
512+
static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
513+
/* NT mV Trans mV db */
514+
{ 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
515+
{ 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
516+
{ 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
517+
{ 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
518+
{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
519+
{ 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
520+
{ 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
521+
{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
522+
{ 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
523+
{ 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
563524
};
564525

565-
/* Voltage Swing Programming for VccIO 1.05V for DP */
566-
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
567-
/* Voltage mV db */
568-
{ 0x2, 0x98, 0x0018 }, /* 400 0.0 */
569-
{ 0x2, 0x98, 0x3015 }, /* 400 3.5 */
570-
{ 0x2, 0x98, 0x6012 }, /* 400 6.0 */
571-
{ 0x2, 0x98, 0x900F }, /* 400 9.5 */
572-
{ 0x4, 0x98, 0x0018 }, /* 600 0.0 */
573-
{ 0x4, 0x98, 0x3015 }, /* 600 3.5 */
574-
{ 0x4, 0x98, 0x6012 }, /* 600 6.0 */
575-
{ 0x5, 0x71, 0x0018 }, /* 800 0.0 */
576-
{ 0x5, 0x71, 0x3015 }, /* 800 3.5 */
577-
{ 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
526+
static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
527+
/* NT mV Trans mV db */
528+
{ 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
529+
{ 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
530+
{ 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
531+
{ 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
532+
{ 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
533+
{ 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
534+
{ 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
535+
{ 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
536+
{ 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
537+
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
578538
};
579539

580-
/* FIXME - After table is updated in Bspec */
581-
/* Voltage Swing Programming for VccIO 1.05V for eDP */
582-
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
583-
/* Voltage mV db */
584-
{ 0x0, 0x00, 0x00 }, /* 200 0.0 */
585-
{ 0x0, 0x00, 0x00 }, /* 200 1.5 */
586-
{ 0x0, 0x00, 0x00 }, /* 200 4.0 */
587-
{ 0x0, 0x00, 0x00 }, /* 200 6.0 */
588-
{ 0x0, 0x00, 0x00 }, /* 250 0.0 */
589-
{ 0x0, 0x00, 0x00 }, /* 250 1.5 */
590-
{ 0x0, 0x00, 0x00 }, /* 250 4.0 */
591-
{ 0x0, 0x00, 0x00 }, /* 300 0.0 */
592-
{ 0x0, 0x00, 0x00 }, /* 300 1.5 */
593-
{ 0x0, 0x00, 0x00 }, /* 350 0.0 */
540+
static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
541+
/* NT mV Trans mV db */
542+
{ 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
543+
{ 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
544+
{ 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
545+
{ 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
546+
{ 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
547+
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
548+
{ 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
594549
};
595550

596551
struct icl_mg_phy_ddi_buf_trans {
@@ -871,43 +826,23 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
871826
}
872827
}
873828

874-
static const struct icl_combo_phy_ddi_buf_trans *
829+
static const struct cnl_ddi_buf_trans *
875830
icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
876-
int type, int *n_entries)
831+
int type, int rate, int *n_entries)
877832
{
878-
u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
879-
880-
if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
881-
switch (voltage) {
882-
case VOLTAGE_INFO_0_85V:
883-
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
884-
return icl_combo_phy_ddi_translations_edp_0_85V;
885-
case VOLTAGE_INFO_0_95V:
886-
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
887-
return icl_combo_phy_ddi_translations_edp_0_95V;
888-
case VOLTAGE_INFO_1_05V:
889-
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
890-
return icl_combo_phy_ddi_translations_edp_1_05V;
891-
default:
892-
MISSING_CASE(voltage);
893-
return NULL;
894-
}
895-
} else {
896-
switch (voltage) {
897-
case VOLTAGE_INFO_0_85V:
898-
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
899-
return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
900-
case VOLTAGE_INFO_0_95V:
901-
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
902-
return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
903-
case VOLTAGE_INFO_1_05V:
904-
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
905-
return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
906-
default:
907-
MISSING_CASE(voltage);
908-
return NULL;
909-
}
833+
if (type == INTEL_OUTPUT_HDMI) {
834+
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
835+
return icl_combo_phy_ddi_translations_hdmi;
836+
} else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
837+
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
838+
return icl_combo_phy_ddi_translations_edp_hbr3;
839+
} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
840+
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
841+
return icl_combo_phy_ddi_translations_edp_hbr2;
910842
}
843+
844+
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
845+
return icl_combo_phy_ddi_translations_dp_hbr2;
911846
}
912847

913848
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
@@ -918,8 +853,8 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
918853

919854
if (IS_ICELAKE(dev_priv)) {
920855
if (intel_port_is_combophy(dev_priv, port))
921-
icl_get_combo_buf_trans(dev_priv, port,
922-
INTEL_OUTPUT_HDMI, &n_entries);
856+
icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
857+
0, &n_entries);
923858
else
924859
n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
925860
default_entry = n_entries - 1;
@@ -2275,13 +2210,14 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
22752210
u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
22762211
{
22772212
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2213+
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
22782214
enum port port = encoder->port;
22792215
int n_entries;
22802216

22812217
if (IS_ICELAKE(dev_priv)) {
22822218
if (intel_port_is_combophy(dev_priv, port))
22832219
icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2284-
&n_entries);
2220+
intel_dp->link_rate, &n_entries);
22852221
else
22862222
n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
22872223
} else if (IS_CANNONLAKE(dev_priv)) {
@@ -2462,14 +2398,15 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
24622398
}
24632399

24642400
static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2465-
u32 level, enum port port, int type)
2401+
u32 level, enum port port, int type,
2402+
int rate)
24662403
{
2467-
const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
2404+
const struct cnl_ddi_buf_trans *ddi_translations = NULL;
24682405
u32 n_entries, val;
24692406
int ln;
24702407

24712408
ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2472-
&n_entries);
2409+
rate, &n_entries);
24732410
if (!ddi_translations)
24742411
return;
24752412

@@ -2478,34 +2415,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
24782415
level = n_entries - 1;
24792416
}
24802417

2481-
/* Set PORT_TX_DW5 Rterm Sel to 110b. */
2418+
/* Set PORT_TX_DW5 */
24822419
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2483-
val &= ~RTERM_SELECT_MASK;
2420+
val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2421+
TAP2_DISABLE | TAP3_DISABLE);
2422+
val |= SCALING_MODE_SEL(0x2);
24842423
val |= RTERM_SELECT(0x6);
2485-
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2486-
2487-
/* Program PORT_TX_DW5 */
2488-
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2489-
/* Set DisableTap2 and DisableTap3 if MIPI DSI
2490-
* Clear DisableTap2 and DisableTap3 for all other Ports
2491-
*/
2492-
if (type == INTEL_OUTPUT_DSI) {
2493-
val |= TAP2_DISABLE;
2494-
val |= TAP3_DISABLE;
2495-
} else {
2496-
val &= ~TAP2_DISABLE;
2497-
val &= ~TAP3_DISABLE;
2498-
}
2424+
val |= TAP3_DISABLE;
24992425
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
25002426

25012427
/* Program PORT_TX_DW2 */
25022428
val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
25032429
val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
25042430
RCOMP_SCALAR_MASK);
2505-
val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
2506-
val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
2431+
val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2432+
val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
25072433
/* Program Rcomp scalar for every table entry */
2508-
val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
2434+
val |= RCOMP_SCALAR(0x98);
25092435
I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
25102436

25112437
/* Program PORT_TX_DW4 */
@@ -2514,9 +2440,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
25142440
val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
25152441
val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
25162442
CURSOR_COEFF_MASK);
2517-
val |= ddi_translations[level].dw4_scaling;
2443+
val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2444+
val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2445+
val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
25182446
I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
25192447
}
2448+
2449+
/* Program PORT_TX_DW7 */
2450+
val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
2451+
val &= ~N_SCALAR_MASK;
2452+
val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2453+
I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
25202454
}
25212455

25222456
static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
@@ -2581,7 +2515,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
25812515
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
25822516

25832517
/* 5. Program swing and de-emphasis */
2584-
icl_ddi_combo_vswing_program(dev_priv, level, port, type);
2518+
icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
25852519

25862520
/* 6. Set training enable to trigger update */
25872521
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));

‎drivers/gpu/drm/i915/intel_dp.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -304,9 +304,11 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
304304
static int icl_max_source_rate(struct intel_dp *intel_dp)
305305
{
306306
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
307+
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
307308
enum port port = dig_port->base.port;
308309

309-
if (port == PORT_B)
310+
if (intel_port_is_combophy(dev_priv, port) &&
311+
!intel_dp_is_edp(intel_dp))
310312
return 540000;
311313

312314
return 810000;

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