Support for ARC770 core introduced with Rel 4.10 (Summer 2011)

This core has a bunch of cool new features:

-MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)

-Caches: New Prog Model, Region Flush

-Insns: endian swap, load-locked/store-conditional, time-stamp-ctr

config ARC_CPU_HS

bool "ARC-HS"

at designated entry point. For other case, all jump to common

entry point and spin wait for Master's signal.

config ARC_MCIP

bool "ARConnect Multicore IP (MCIP) Support "

bool "Support VIPT Aliasing D$"

depends on ARC_HAS_DCACHE && ISA_ARCOMPACT

config ARC_HAS_ICCM

bool "Use ICCM"

based on actual usage of FPU by a task. Thus our implemn does

this for all tasks in system.

config ARC_CANT_LLSC

def_bool n

This is programmable and can be optionally disabled in which case

software INTERRUPT_PROLOGUE/EPILGUE do the needed work

endmenu # "ARC CPU Configuration"

help

Here we add new hierarchy for CPUs topology.

We got:

At the new thread level each CPU represent one HW thread.

At highest hierarchy each core contain 16 threads,

any of them seem like CPU from Linux point of view.

All threads within same core share the execution unit of the

core and HW scheduler round robin between them.

config EZNPS_MEM_ERROR_ALIGN

On the real chip of the NPS, user memory errors are handled

as a machine check exception, which is fatal, whereas on

simulator platform for NPS, is handled as a Level 2 interrupt