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nbd168paulburton
nbd168
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MIPS: ath79: pass PLL base to clock init functions
Preparation for passing the mapped base via DT Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org
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‎arch/mips/ath79/clock.c

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,7 @@ static struct clk * __init ath79_set_ff_clk(int type, const char *parent,
8080
return clk;
8181
}
8282

83-
static void __init ar71xx_clocks_init(void)
83+
static void __init ar71xx_clocks_init(void __iomem *pll_base)
8484
{
8585
unsigned long ref_rate;
8686
unsigned long cpu_rate;
@@ -92,7 +92,7 @@ static void __init ar71xx_clocks_init(void)
9292

9393
ref_rate = AR71XX_BASE_FREQ;
9494

95-
pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
95+
pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
9696

9797
div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
9898
freq = div * ref_rate;
@@ -130,13 +130,13 @@ static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
130130
ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
131131
}
132132

133-
static void __init ar724x_clocks_init(void)
133+
static void __init ar724x_clocks_init(void __iomem *pll_base)
134134
{
135135
struct clk *ref_clk;
136136

137137
ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
138138

139-
ar724x_clk_init(ref_clk, ath79_pll_base);
139+
ar724x_clk_init(ref_clk, pll_base);
140140
}
141141

142142
static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
@@ -197,7 +197,7 @@ static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
197197
ref_div * out_div * ahb_div);
198198
}
199199

200-
static void __init ar933x_clocks_init(void)
200+
static void __init ar933x_clocks_init(void __iomem *pll_base)
201201
{
202202
struct clk *ref_clk;
203203
unsigned long ref_rate;
@@ -234,7 +234,7 @@ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
234234
return ret;
235235
}
236236

237-
static void __init ar934x_clocks_init(void)
237+
static void __init ar934x_clocks_init(void __iomem *pll_base)
238238
{
239239
unsigned long ref_rate;
240240
unsigned long cpu_rate;
@@ -265,7 +265,7 @@ static void __init ar934x_clocks_init(void)
265265
AR934X_SRIF_DPLL1_REFDIV_MASK;
266266
frac = 1 << 18;
267267
} else {
268-
pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
268+
pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
269269
out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
270270
AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
271271
ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
@@ -292,7 +292,7 @@ static void __init ar934x_clocks_init(void)
292292
AR934X_SRIF_DPLL1_REFDIV_MASK;
293293
frac = 1 << 18;
294294
} else {
295-
pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
295+
pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
296296
out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
297297
AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
298298
ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
@@ -307,7 +307,7 @@ static void __init ar934x_clocks_init(void)
307307
ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
308308
nfrac, frac, out_div);
309309

310-
clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
310+
clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
311311

312312
postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
313313
AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
@@ -347,7 +347,7 @@ static void __init ar934x_clocks_init(void)
347347
iounmap(dpll_base);
348348
}
349349

350-
static void __init qca953x_clocks_init(void)
350+
static void __init qca953x_clocks_init(void __iomem *pll_base)
351351
{
352352
unsigned long ref_rate;
353353
unsigned long cpu_rate;
@@ -363,7 +363,7 @@ static void __init qca953x_clocks_init(void)
363363
else
364364
ref_rate = 25 * 1000 * 1000;
365365

366-
pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
366+
pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
367367
out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
368368
QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
369369
ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
@@ -377,7 +377,7 @@ static void __init qca953x_clocks_init(void)
377377
cpu_pll += frac * (ref_rate >> 6) / ref_div;
378378
cpu_pll /= (1 << out_div);
379379

380-
pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
380+
pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
381381
out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
382382
QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
383383
ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
@@ -391,7 +391,7 @@ static void __init qca953x_clocks_init(void)
391391
ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
392392
ddr_pll /= (1 << out_div);
393393

394-
clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
394+
clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
395395

396396
postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
397397
QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
@@ -429,7 +429,7 @@ static void __init qca953x_clocks_init(void)
429429
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
430430
}
431431

432-
static void __init qca955x_clocks_init(void)
432+
static void __init qca955x_clocks_init(void __iomem *pll_base)
433433
{
434434
unsigned long ref_rate;
435435
unsigned long cpu_rate;
@@ -445,7 +445,7 @@ static void __init qca955x_clocks_init(void)
445445
else
446446
ref_rate = 25 * 1000 * 1000;
447447

448-
pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
448+
pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
449449
out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
450450
QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
451451
ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
@@ -459,7 +459,7 @@ static void __init qca955x_clocks_init(void)
459459
cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
460460
cpu_pll /= (1 << out_div);
461461

462-
pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
462+
pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
463463
out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
464464
QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
465465
ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
@@ -473,7 +473,7 @@ static void __init qca955x_clocks_init(void)
473473
ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
474474
ddr_pll /= (1 << out_div);
475475

476-
clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
476+
clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
477477

478478
postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
479479
QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
@@ -511,7 +511,7 @@ static void __init qca955x_clocks_init(void)
511511
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
512512
}
513513

514-
static void __init qca956x_clocks_init(void)
514+
static void __init qca956x_clocks_init(void __iomem *pll_base)
515515
{
516516
unsigned long ref_rate;
517517
unsigned long cpu_rate;
@@ -537,13 +537,13 @@ static void __init qca956x_clocks_init(void)
537537
else
538538
ref_rate = 25 * 1000 * 1000;
539539

540-
pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
540+
pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
541541
out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
542542
QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
543543
ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
544544
QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
545545

546-
pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
546+
pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
547547
nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
548548
QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
549549
hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
@@ -556,12 +556,12 @@ static void __init qca956x_clocks_init(void)
556556
cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
557557
cpu_pll /= (1 << out_div);
558558

559-
pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
559+
pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
560560
out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
561561
QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
562562
ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
563563
QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
564-
pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
564+
pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
565565
nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
566566
QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
567567
hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
@@ -574,7 +574,7 @@ static void __init qca956x_clocks_init(void)
574574
ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
575575
ddr_pll /= (1 << out_div);
576576

577-
clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
577+
clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
578578

579579
postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
580580
QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
@@ -618,19 +618,19 @@ void __init ath79_clocks_init(void)
618618
const char *uart;
619619

620620
if (soc_is_ar71xx())
621-
ar71xx_clocks_init();
621+
ar71xx_clocks_init(ath79_pll_base);
622622
else if (soc_is_ar724x() || soc_is_ar913x())
623-
ar724x_clocks_init();
623+
ar724x_clocks_init(ath79_pll_base);
624624
else if (soc_is_ar933x())
625-
ar933x_clocks_init();
625+
ar933x_clocks_init(ath79_pll_base);
626626
else if (soc_is_ar934x())
627-
ar934x_clocks_init();
627+
ar934x_clocks_init(ath79_pll_base);
628628
else if (soc_is_qca953x())
629-
qca953x_clocks_init();
629+
qca953x_clocks_init(ath79_pll_base);
630630
else if (soc_is_qca955x())
631-
qca955x_clocks_init();
631+
qca955x_clocks_init(ath79_pll_base);
632632
else if (soc_is_qca956x() || soc_is_tp9343())
633-
qca956x_clocks_init();
633+
qca956x_clocks_init(ath79_pll_base);
634634
else
635635
BUG();
636636

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