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MIPS: ath79: add helpers for setting clocks and expose the ref clock
Preparation for transitioning the legacy clock setup code over to OF. Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: John Crispin <john@phrozen.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org
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-63
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‎arch/mips/ath79/clock.c

Lines changed: 66 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -37,20 +37,46 @@ static struct clk_onecell_data clk_data = {
3737
.clk_num = ARRAY_SIZE(clks),
3838
};
3939

40-
static struct clk *__init ath79_add_sys_clkdev(
41-
const char *id, unsigned long rate)
40+
static const char * const clk_names[ATH79_CLK_END] = {
41+
[ATH79_CLK_CPU] = "cpu",
42+
[ATH79_CLK_DDR] = "ddr",
43+
[ATH79_CLK_AHB] = "ahb",
44+
[ATH79_CLK_REF] = "ref",
45+
};
46+
47+
static const char * __init ath79_clk_name(int type)
4248
{
43-
struct clk *clk;
44-
int err;
49+
BUG_ON(type >= ARRAY_SIZE(clk_names) || !clk_names[type]);
50+
return clk_names[type];
51+
}
4552

46-
clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
53+
static void __init __ath79_set_clk(int type, const char *name, struct clk *clk)
54+
{
4755
if (IS_ERR(clk))
48-
panic("failed to allocate %s clock structure", id);
56+
panic("failed to allocate %s clock structure", clk_names[type]);
4957

50-
err = clk_register_clkdev(clk, id, NULL);
51-
if (err)
52-
panic("unable to register %s clock device", id);
58+
clks[type] = clk;
59+
clk_register_clkdev(clk, name, NULL);
60+
}
5361

62+
static struct clk * __init ath79_set_clk(int type, unsigned long rate)
63+
{
64+
const char *name = ath79_clk_name(type);
65+
struct clk *clk;
66+
67+
clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate);
68+
__ath79_set_clk(type, name, clk);
69+
return clk;
70+
}
71+
72+
static struct clk * __init ath79_set_ff_clk(int type, const char *parent,
73+
unsigned int mult, unsigned int div)
74+
{
75+
const char *name = ath79_clk_name(type);
76+
struct clk *clk;
77+
78+
clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div);
79+
__ath79_set_clk(type, name, clk);
5480
return clk;
5581
}
5682

@@ -80,27 +106,15 @@ static void __init ar71xx_clocks_init(void)
80106
div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
81107
ahb_rate = cpu_rate / div;
82108

83-
ath79_add_sys_clkdev("ref", ref_rate);
84-
clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
85-
clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
86-
clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
109+
ath79_set_clk(ATH79_CLK_REF, ref_rate);
110+
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
111+
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
112+
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
87113

88114
clk_add_alias("wdt", NULL, "ahb", NULL);
89115
clk_add_alias("uart", NULL, "ahb", NULL);
90116
}
91117

92-
static struct clk * __init ath79_reg_ffclk(const char *name,
93-
const char *parent_name, unsigned int mult, unsigned int div)
94-
{
95-
struct clk *clk;
96-
97-
clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
98-
if (IS_ERR(clk))
99-
panic("failed to allocate %s clock structure", name);
100-
101-
return clk;
102-
}
103-
104118
static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
105119
{
106120
u32 pll;
@@ -114,24 +128,19 @@ static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
114128
ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
115129
ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
116130

117-
clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
118-
clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
119-
clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
131+
ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div);
132+
ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div);
133+
ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
120134
}
121135

122136
static void __init ar724x_clocks_init(void)
123137
{
124138
struct clk *ref_clk;
125139

126-
ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
140+
ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
127141

128142
ar724x_clk_init(ref_clk, ath79_pll_base);
129143

130-
/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
131-
clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
132-
clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
133-
clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
134-
135144
clk_add_alias("wdt", NULL, "ahb", NULL);
136145
clk_add_alias("uart", NULL, "ahb", NULL);
137146
}
@@ -186,12 +195,12 @@ static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
186195
AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
187196
}
188197

189-
clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
190-
ninit_mul, ref_div * out_div * cpu_div);
191-
clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
192-
ninit_mul, ref_div * out_div * ddr_div);
193-
clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
194-
ninit_mul, ref_div * out_div * ahb_div);
198+
ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul,
199+
ref_div * out_div * cpu_div);
200+
ath79_set_ff_clk(ATH79_CLK_DDR, "ref", ninit_mul,
201+
ref_div * out_div * ddr_div);
202+
ath79_set_ff_clk(ATH79_CLK_AHB, "ref", ninit_mul,
203+
ref_div * out_div * ahb_div);
195204
}
196205

197206
static void __init ar933x_clocks_init(void)
@@ -206,15 +215,10 @@ static void __init ar933x_clocks_init(void)
206215
else
207216
ref_rate = (25 * 1000 * 1000);
208217

209-
ref_clk = ath79_add_sys_clkdev("ref", ref_rate);
218+
ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
210219

211220
ar9330_clk_init(ref_clk, ath79_pll_base);
212221

213-
/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
214-
clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
215-
clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
216-
clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
217-
218222
clk_add_alias("wdt", NULL, "ahb", NULL);
219223
clk_add_alias("uart", NULL, "ref", NULL);
220224
}
@@ -344,10 +348,10 @@ static void __init ar934x_clocks_init(void)
344348
else
345349
ahb_rate = cpu_pll / (postdiv + 1);
346350

347-
ath79_add_sys_clkdev("ref", ref_rate);
348-
clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
349-
clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
350-
clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
351+
ath79_set_clk(ATH79_CLK_REF, ref_rate);
352+
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
353+
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
354+
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
351355

352356
clk_add_alias("wdt", NULL, "ref", NULL);
353357
clk_add_alias("uart", NULL, "ref", NULL);
@@ -431,10 +435,10 @@ static void __init qca953x_clocks_init(void)
431435
else
432436
ahb_rate = cpu_pll / (postdiv + 1);
433437

434-
ath79_add_sys_clkdev("ref", ref_rate);
435-
ath79_add_sys_clkdev("cpu", cpu_rate);
436-
ath79_add_sys_clkdev("ddr", ddr_rate);
437-
ath79_add_sys_clkdev("ahb", ahb_rate);
438+
ath79_set_clk(ATH79_CLK_REF, ref_rate);
439+
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
440+
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
441+
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
438442

439443
clk_add_alias("wdt", NULL, "ref", NULL);
440444
clk_add_alias("uart", NULL, "ref", NULL);
@@ -516,10 +520,10 @@ static void __init qca955x_clocks_init(void)
516520
else
517521
ahb_rate = cpu_pll / (postdiv + 1);
518522

519-
ath79_add_sys_clkdev("ref", ref_rate);
520-
clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
521-
clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
522-
clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
523+
ath79_set_clk(ATH79_CLK_REF, ref_rate);
524+
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
525+
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
526+
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
523527

524528
clk_add_alias("wdt", NULL, "ref", NULL);
525529
clk_add_alias("uart", NULL, "ref", NULL);
@@ -620,10 +624,10 @@ static void __init qca956x_clocks_init(void)
620624
else
621625
ahb_rate = cpu_pll / (postdiv + 1);
622626

623-
ath79_add_sys_clkdev("ref", ref_rate);
624-
ath79_add_sys_clkdev("cpu", cpu_rate);
625-
ath79_add_sys_clkdev("ddr", ddr_rate);
626-
ath79_add_sys_clkdev("ahb", ahb_rate);
627+
ath79_set_clk(ATH79_CLK_REF, ref_rate);
628+
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
629+
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
630+
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
627631

628632
clk_add_alias("wdt", NULL, "ref", NULL);
629633
clk_add_alias("uart", NULL, "ref", NULL);

‎include/dt-bindings/clock/ath79-clk.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,8 @@
1313
#define ATH79_CLK_CPU 0
1414
#define ATH79_CLK_DDR 1
1515
#define ATH79_CLK_AHB 2
16+
#define ATH79_CLK_REF 3
1617

17-
#define ATH79_CLK_END 3
18+
#define ATH79_CLK_END 4
1819

1920
#endif /* __DT_BINDINGS_ATH79_CLK_H */

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