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Marc Zyngier
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irqchip/gic: Drop support for secondary GIC in non-DT systems
We do not have any in-tree platform with this pathological setup, and only a single system (Cavium's cns3xxx) isn't DT aware. Let's drop the secondary GIC support for now, until we remove the above horror altogether. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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3 files changed

+18
-32
lines changed

3 files changed

+18
-32
lines changed

‎arch/arm/mach-cns3xxx/core.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@ void __init cns3xxx_map_io(void)
9090
/* used by entry-macro.S */
9191
void __init cns3xxx_init_irq(void)
9292
{
93-
gic_init(0, 29, IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
93+
gic_init(IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
9494
IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
9595
}
9696

‎drivers/irqchip/irq-gic.c

Lines changed: 16 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1089,11 +1089,10 @@ static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
10891089
#endif
10901090
}
10911091

1092-
static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
1092+
static int gic_init_bases(struct gic_chip_data *gic,
10931093
struct fwnode_handle *handle)
10941094
{
1095-
irq_hw_number_t hwirq_base;
1096-
int gic_irqs, irq_base, ret;
1095+
int gic_irqs, ret;
10971096

10981097
if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
10991098
/* Frankein-GIC without banked registers... */
@@ -1145,28 +1144,21 @@ static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
11451144
} else { /* Legacy support */
11461145
/*
11471146
* For primary GICs, skip over SGIs.
1148-
* For secondary GICs, skip over PPIs, too.
1147+
* No secondary GIC support whatsoever.
11491148
*/
1150-
if (gic == &gic_data[0] && (irq_start & 31) > 0) {
1151-
hwirq_base = 16;
1152-
if (irq_start != -1)
1153-
irq_start = (irq_start & ~31) + 16;
1154-
} else {
1155-
hwirq_base = 32;
1156-
}
1149+
int irq_base;
11571150

1158-
gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
1151+
gic_irqs -= 16; /* calculate # of irqs to allocate */
11591152

1160-
irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1153+
irq_base = irq_alloc_descs(16, 16, gic_irqs,
11611154
numa_node_id());
11621155
if (irq_base < 0) {
1163-
WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1164-
irq_start);
1165-
irq_base = irq_start;
1156+
WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n");
1157+
irq_base = 16;
11661158
}
11671159

11681160
gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1169-
hwirq_base, &gic_irq_domain_ops, gic);
1161+
16, &gic_irq_domain_ops, gic);
11701162
}
11711163

11721164
if (WARN_ON(!gic->domain)) {
@@ -1195,7 +1187,6 @@ static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
11951187
}
11961188

11971189
static int __init __gic_init_bases(struct gic_chip_data *gic,
1198-
int irq_start,
11991190
struct fwnode_handle *handle)
12001191
{
12011192
char *name;
@@ -1231,32 +1222,28 @@ static int __init __gic_init_bases(struct gic_chip_data *gic,
12311222
gic_init_chip(gic, NULL, name, false);
12321223
}
12331224

1234-
ret = gic_init_bases(gic, irq_start, handle);
1225+
ret = gic_init_bases(gic, handle);
12351226
if (ret)
12361227
kfree(name);
12371228

12381229
return ret;
12391230
}
12401231

1241-
void __init gic_init(unsigned int gic_nr, int irq_start,
1242-
void __iomem *dist_base, void __iomem *cpu_base)
1232+
void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base)
12431233
{
12441234
struct gic_chip_data *gic;
12451235

1246-
if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR))
1247-
return;
1248-
12491236
/*
12501237
* Non-DT/ACPI systems won't run a hypervisor, so let's not
12511238
* bother with these...
12521239
*/
12531240
static_branch_disable(&supports_deactivate_key);
12541241

1255-
gic = &gic_data[gic_nr];
1242+
gic = &gic_data[0];
12561243
gic->raw_dist_base = dist_base;
12571244
gic->raw_cpu_base = cpu_base;
12581245

1259-
__gic_init_bases(gic, irq_start, NULL);
1246+
__gic_init_bases(gic, NULL);
12601247
}
12611248

12621249
static void gic_teardown(struct gic_chip_data *gic)
@@ -1399,7 +1386,7 @@ int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
13991386
if (ret)
14001387
return ret;
14011388

1402-
ret = gic_init_bases(*gic, -1, &dev->of_node->fwnode);
1389+
ret = gic_init_bases(*gic, &dev->of_node->fwnode);
14031390
if (ret) {
14041391
gic_teardown(*gic);
14051392
return ret;
@@ -1459,7 +1446,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
14591446
if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
14601447
static_branch_disable(&supports_deactivate_key);
14611448

1462-
ret = __gic_init_bases(gic, -1, &node->fwnode);
1449+
ret = __gic_init_bases(gic, &node->fwnode);
14631450
if (ret) {
14641451
gic_teardown(gic);
14651452
return ret;
@@ -1650,7 +1637,7 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
16501637
return -ENOMEM;
16511638
}
16521639

1653-
ret = __gic_init_bases(gic, -1, domain_handle);
1640+
ret = __gic_init_bases(gic, domain_handle);
16541641
if (ret) {
16551642
pr_err("Failed to initialise GIC\n");
16561643
irq_domain_free_fwnode(domain_handle);

‎include/linux/irqchip/arm-gic.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -158,8 +158,7 @@ int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq);
158158
* Legacy platforms not converted to DT yet must use this to init
159159
* their GIC
160160
*/
161-
void gic_init(unsigned int nr, int start,
162-
void __iomem *dist , void __iomem *cpu);
161+
void gic_init(void __iomem *dist , void __iomem *cpu);
163162

164163
int gicv2m_init(struct fwnode_handle *parent_handle,
165164
struct irq_domain *parent);

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