PCI: cadence: Write MSI data with 32bits

Alan Douglas · Lorenzo Pieralisi · commit e81e36a96bb5 · 2018-10-12T12:09:29.000+01:00
According to the PCIe specification, although the MSI data is only 16bits, the upper 16bits should be written as 0. Use writel instead of writew when writing the MSI data to the host. Fixes: 37dddf1 ("PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller") Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
@@ -355,7 +355,7 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
 		ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
 		ep->irq_pci_fn = fn;
 	}
-	writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
+	writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
 
 	return 0;
 }

Original file line number	Diff line number	Diff line change
`@@ -355,7 +355,7 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,`
`355`	`355`	`ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);`
`356`	`356`	`ep->irq_pci_fn = fn;`
`357`	`357`	`}`
`358`		`- writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));`
	`358`	`+ writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));`
`359`	`359`
`360`	`360`	`return 0;`
`361`	`361`	`}`