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bjorn-helgaasbjorn-helgaas
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Merge branch 'pci/misc'
 - Remove unused Netronome NFP32xx Device IDs (Jakub Kicinski) - Use bitmap_zalloc() for dma_alias_mask (Andy Shevchenko) - Add switch fall-through annotations (Gustavo A. R. Silva) - Remove unused Switchtec quirk variable (Joshua Abraham) - Fix pci.c kernel-doc warning (Randy Dunlap) - Remove trivial PCI wrappers for DMA APIs (Christoph Hellwig) - Add Intel GPU device IDs to spurious interrupt quirk (Bin Meng) - Run Switchtec DMA aliasing quirk only on NTB endpoints to avoid useless dmesg errors (Logan Gunthorpe) - Update Switchtec NTB documentation (Wesley Yung) - Remove redundant "default n" from Kconfig (Bartlomiej Zolnierkiewicz) * pci/misc: PCI: pcie: Remove redundant 'default n' from Kconfig NTB: switchtec_ntb: Update switchtec documentation with prerequisites for NTB PCI: Fix Switchtec DMA aliasing quirk dmesg noise PCI: Add macro for Switchtec quirk declarations PCI: Add Device IDs for Intel GPU "spurious interrupt" quirk PCI: Remove pci_set_dma_max_seg_size() PCI: Remove pci_set_dma_seg_boundary() PCI: Remove pci_unmap_addr() wrappers for DMA API PCI / ACPI: Mark expected switch fall-through PCI: Remove set but unused variable PCI: Fix pci.c kernel-doc parameter warning PCI: Allocate dma_alias_mask with bitmap_zalloc() PCI: Remove unused NFP32xx IDs
2 parents 20634dc + fe73c23 commit ee8360f

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16 files changed

+75
-122
lines changed

16 files changed

+75
-122
lines changed

‎Documentation/switchtec.txt

Lines changed: 20 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ The primary means of communicating with the Switchtec management firmware is
2323
through the Memory-mapped Remote Procedure Call (MRPC) interface.
2424
Commands are submitted to the interface with a 4-byte command
2525
identifier and up to 1KB of command specific data. The firmware will
26-
respond with a 4 bytes return code and up to 1KB of command specific
26+
respond with a 4-byte return code and up to 1KB of command-specific
2727
data. The interface only processes a single command at a time.
2828

2929

@@ -36,18 +36,18 @@ device: /dev/switchtec#, one for each management endpoint in the system.
3636
The char device has the following semantics:
3737

3838
* A write must consist of at least 4 bytes and no more than 1028 bytes.
39-
The first four bytes will be interpreted as the command to run and
40-
the remainder will be used as the input data. A write will send the
39+
The first 4 bytes will be interpreted as the Command ID and the
40+
remainder will be used as the input data. A write will send the
4141
command to the firmware to begin processing.
4242

4343
* Each write must be followed by exactly one read. Any double write will
4444
produce an error and any read that doesn't follow a write will
4545
produce an error.
4646

4747
* A read will block until the firmware completes the command and return
48-
the four bytes of status plus up to 1024 bytes of output data. (The
49-
length will be specified by the size parameter of the read call --
50-
reading less than 4 bytes will produce an error.
48+
the 4-byte Command Return Value plus up to 1024 bytes of output
49+
data. (The length will be specified by the size parameter of the read
50+
call -- reading less than 4 bytes will produce an error.)
5151

5252
* The poll call will also be supported for userspace applications that
5353
need to do other things while waiting for the command to complete.
@@ -83,10 +83,20 @@ The following IOCTLs are also supported by the device:
8383
Non-Transparent Bridge (NTB) Driver
8484
===================================
8585

86-
An NTB driver is provided for the switchtec hardware in switchtec_ntb.
87-
Currently, it only supports switches configured with exactly 2
88-
partitions. It also requires the following configuration settings:
86+
An NTB hardware driver is provided for the Switchtec hardware in
87+
ntb_hw_switchtec. Currently, it only supports switches configured with
88+
exactly 2 NT partitions and zero or more non-NT partitions. It also requires
89+
the following configuration settings:
8990

90-
* Both partitions must be able to access each other's GAS spaces.
91+
* Both NT partitions must be able to access each other's GAS spaces.
9192
Thus, the bits in the GAS Access Vector under Management Settings
9293
must be set to support this.
94+
* Kernel configuration MUST include support for NTB (CONFIG_NTB needs
95+
to be set)
96+
97+
NT EP BAR 2 will be dynamically configured as a Direct Window, and
98+
the configuration file does not need to configure it explicitly.
99+
100+
Please refer to Documentation/ntb.txt in Linux source tree for an overall
101+
understanding of the Linux NTB stack. ntb_hw_switchtec works as an NTB
102+
Hardware Driver in this stack.

‎drivers/ata/sata_inic162x.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -873,7 +873,7 @@ static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
873873
* like others but it will lock up the whole machine HARD if
874874
* 65536 byte PRD entry is fed. Reduce maximum segment size.
875875
*/
876-
rc = pci_set_dma_max_seg_size(pdev, 65536 - 512);
876+
rc = dma_set_max_seg_size(&pdev->dev, 65536 - 512);
877877
if (rc) {
878878
dev_err(&pdev->dev, "failed to set the maximum segment size\n");
879879
return rc;

‎drivers/block/rsxx/core.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -780,7 +780,7 @@ static int rsxx_pci_probe(struct pci_dev *dev,
780780
goto failed_enable;
781781

782782
pci_set_master(dev);
783-
pci_set_dma_max_seg_size(dev, RSXX_HW_BLK_SIZE);
783+
dma_set_max_seg_size(&dev->dev, RSXX_HW_BLK_SIZE);
784784

785785
st = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
786786
if (st) {

‎drivers/infiniband/hw/cxgb4/qp.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,7 @@ static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
9999
static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
100100
{
101101
dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
102-
pci_unmap_addr(sq, mapping));
102+
dma_unmap_addr(sq, mapping));
103103
}
104104

105105
static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
@@ -132,7 +132,7 @@ static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
132132
if (!sq->queue)
133133
return -ENOMEM;
134134
sq->phys_addr = virt_to_phys(sq->queue);
135-
pci_unmap_addr_set(sq, mapping, sq->dma_addr);
135+
dma_unmap_addr_set(sq, mapping, sq->dma_addr);
136136
return 0;
137137
}
138138

@@ -2521,7 +2521,7 @@ static void free_srq_queue(struct c4iw_srq *srq, struct c4iw_dev_ucontext *uctx,
25212521

25222522
dma_free_coherent(&rdev->lldi.pdev->dev,
25232523
wq->memsize, wq->queue,
2524-
pci_unmap_addr(wq, mapping));
2524+
dma_unmap_addr(wq, mapping));
25252525
c4iw_rqtpool_free(rdev, wq->rqt_hwaddr, wq->rqt_size);
25262526
kfree(wq->sw_rq);
25272527
c4iw_put_qpid(rdev, wq->qid, uctx);
@@ -2570,7 +2570,7 @@ static int alloc_srq_queue(struct c4iw_srq *srq, struct c4iw_dev_ucontext *uctx,
25702570
goto err_free_rqtpool;
25712571

25722572
memset(wq->queue, 0, wq->memsize);
2573-
pci_unmap_addr_set(wq, mapping, wq->dma_addr);
2573+
dma_unmap_addr_set(wq, mapping, wq->dma_addr);
25742574

25752575
wq->bar2_va = c4iw_bar2_addrs(rdev, wq->qid, T4_BAR2_QTYPE_EGRESS,
25762576
&wq->bar2_qid,
@@ -2649,7 +2649,7 @@ static int alloc_srq_queue(struct c4iw_srq *srq, struct c4iw_dev_ucontext *uctx,
26492649
err_free_queue:
26502650
dma_free_coherent(&rdev->lldi.pdev->dev,
26512651
wq->memsize, wq->queue,
2652-
pci_unmap_addr(wq, mapping));
2652+
dma_unmap_addr(wq, mapping));
26532653
err_free_rqtpool:
26542654
c4iw_rqtpool_free(rdev, wq->rqt_hwaddr, wq->rqt_size);
26552655
err_free_pending_wrs:

‎drivers/infiniband/hw/cxgb4/t4.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -397,7 +397,7 @@ struct t4_srq_pending_wr {
397397
struct t4_srq {
398398
union t4_recv_wr *queue;
399399
dma_addr_t dma_addr;
400-
DECLARE_PCI_UNMAP_ADDR(mapping);
400+
DEFINE_DMA_UNMAP_ADDR(mapping);
401401
struct t4_swrqe *sw_rq;
402402
void __iomem *bar2_va;
403403
u64 bar2_pa;

‎drivers/pci/pci-acpi.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -588,6 +588,7 @@ static int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
588588
error = -EBUSY;
589589
break;
590590
}
591+
/* Fall through */
591592
case PCI_D0:
592593
case PCI_D1:
593594
case PCI_D2:

‎drivers/pci/pci.c

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -198,7 +198,7 @@ EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
198198
/**
199199
* pci_dev_str_match_path - test if a path string matches a device
200200
* @dev: the PCI device to test
201-
* @p: string to match the device against
201+
* @path: string to match the device against
202202
* @endptr: pointer to the string after the match
203203
*
204204
* Test if a string (typically from a kernel parameter) formatted as a
@@ -5773,8 +5773,7 @@ int pci_set_vga_state(struct pci_dev *dev, bool decode,
57735773
void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
57745774
{
57755775
if (!dev->dma_alias_mask)
5776-
dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
5777-
sizeof(long), GFP_KERNEL);
5776+
dev->dma_alias_mask = bitmap_zalloc(U8_MAX, GFP_KERNEL);
57785777
if (!dev->dma_alias_mask) {
57795778
pci_warn(dev, "Unable to allocate DMA alias mask\n");
57805779
return;

‎drivers/pci/pcie/Kconfig

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,6 @@ config PCIEAER
3636
config PCIEAER_INJECT
3737
tristate "PCI Express error injection support"
3838
depends on PCIEAER
39-
default n
4039
help
4140
This enables PCI Express Root Port Advanced Error Reporting
4241
(AER) software error injector.
@@ -84,7 +83,6 @@ config PCIEASPM
8483
config PCIEASPM_DEBUG
8584
bool "Debug PCI Express ASPM"
8685
depends on PCIEASPM
87-
default n
8886
help
8987
This enables PCI Express ASPM debug support. It will add per-device
9088
interface to control ASPM.
@@ -129,7 +127,6 @@ config PCIE_PME
129127
config PCIE_DPC
130128
bool "PCI Express Downstream Port Containment support"
131129
depends on PCIEPORTBUS && PCIEAER
132-
default n
133130
help
134131
This enables PCI Express Downstream Port Containment (DPC)
135132
driver support. DPC events from Root and Downstream ports
@@ -139,7 +136,6 @@ config PCIE_DPC
139136

140137
config PCIE_PTM
141138
bool "PCI Express Precision Time Measurement support"
142-
default n
143139
depends on PCIEPORTBUS
144140
help
145141
This enables PCI Express Precision Time Measurement (PTM)

‎drivers/pci/probe.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2144,7 +2144,7 @@ static void pci_release_dev(struct device *dev)
21442144
pcibios_release_device(pci_dev);
21452145
pci_bus_put(pci_dev->bus);
21462146
kfree(pci_dev->driver_override);
2147-
kfree(pci_dev->dma_alias_mask);
2147+
bitmap_free(pci_dev->dma_alias_mask);
21482148
kfree(pci_dev);
21492149
}
21502150

@@ -2398,8 +2398,8 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
23982398
dev->dev.dma_parms = &dev->dma_parms;
23992399
dev->dev.coherent_dma_mask = 0xffffffffull;
24002400

2401-
pci_set_dma_max_seg_size(dev, 65536);
2402-
pci_set_dma_seg_boundary(dev, 0xffffffff);
2401+
dma_set_max_seg_size(&dev->dev, 65536);
2402+
dma_set_seg_boundary(&dev->dev, 0xffffffff);
24032403

24042404
/* Fix up broken headers */
24052405
pci_fixup_device(pci_fixup_header, dev);

‎drivers/pci/quirks.c

Lines changed: 38 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -3190,7 +3190,11 @@ static void disable_igfx_irq(struct pci_dev *dev)
31903190

31913191
pci_iounmap(dev, regs);
31923192
}
3193+
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3194+
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3195+
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
31933196
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3197+
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
31943198
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
31953199
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
31963200

@@ -4987,7 +4991,6 @@ static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
49874991
void __iomem *mmio;
49884992
struct ntb_info_regs __iomem *mmio_ntb;
49894993
struct ntb_ctrl_regs __iomem *mmio_ctrl;
4990-
struct sys_info_regs __iomem *mmio_sys_info;
49914994
u64 partition_map;
49924995
u8 partition;
49934996
int pp;
@@ -5008,7 +5011,6 @@ static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
50085011

50095012
mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
50105013
mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5011-
mmio_sys_info = mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET;
50125014

50135015
partition = ioread8(&mmio_ntb->partition_id);
50145016

@@ -5057,59 +5059,37 @@ static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
50575059
pci_iounmap(pdev, mmio);
50585060
pci_disable_device(pdev);
50595061
}
5060-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8531,
5061-
quirk_switchtec_ntb_dma_alias);
5062-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8532,
5063-
quirk_switchtec_ntb_dma_alias);
5064-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8533,
5065-
quirk_switchtec_ntb_dma_alias);
5066-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8534,
5067-
quirk_switchtec_ntb_dma_alias);
5068-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8535,
5069-
quirk_switchtec_ntb_dma_alias);
5070-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8536,
5071-
quirk_switchtec_ntb_dma_alias);
5072-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8543,
5073-
quirk_switchtec_ntb_dma_alias);
5074-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8544,
5075-
quirk_switchtec_ntb_dma_alias);
5076-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8545,
5077-
quirk_switchtec_ntb_dma_alias);
5078-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8546,
5079-
quirk_switchtec_ntb_dma_alias);
5080-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8551,
5081-
quirk_switchtec_ntb_dma_alias);
5082-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8552,
5083-
quirk_switchtec_ntb_dma_alias);
5084-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8553,
5085-
quirk_switchtec_ntb_dma_alias);
5086-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8554,
5087-
quirk_switchtec_ntb_dma_alias);
5088-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8555,
5089-
quirk_switchtec_ntb_dma_alias);
5090-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8556,
5091-
quirk_switchtec_ntb_dma_alias);
5092-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8561,
5093-
quirk_switchtec_ntb_dma_alias);
5094-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8562,
5095-
quirk_switchtec_ntb_dma_alias);
5096-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8563,
5097-
quirk_switchtec_ntb_dma_alias);
5098-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8564,
5099-
quirk_switchtec_ntb_dma_alias);
5100-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8565,
5101-
quirk_switchtec_ntb_dma_alias);
5102-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8566,
5103-
quirk_switchtec_ntb_dma_alias);
5104-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8571,
5105-
quirk_switchtec_ntb_dma_alias);
5106-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8572,
5107-
quirk_switchtec_ntb_dma_alias);
5108-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8573,
5109-
quirk_switchtec_ntb_dma_alias);
5110-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8574,
5111-
quirk_switchtec_ntb_dma_alias);
5112-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8575,
5113-
quirk_switchtec_ntb_dma_alias);
5114-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8576,
5115-
quirk_switchtec_ntb_dma_alias);
5062+
#define SWITCHTEC_QUIRK(vid) \
5063+
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5064+
PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5065+
5066+
SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5067+
SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5068+
SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5069+
SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5070+
SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5071+
SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5072+
SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5073+
SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5074+
SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5075+
SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5076+
SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5077+
SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5078+
SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5079+
SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5080+
SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5081+
SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5082+
SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5083+
SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5084+
SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5085+
SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5086+
SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5087+
SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5088+
SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5089+
SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5090+
SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5091+
SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5092+
SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5093+
SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5094+
SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5095+
SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */

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