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airliedairlied
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Merge branch 'drm-next-5.1' of git://people.freedesktop.org/~agd5f/linux into drm-next
Updates for 5.1: - GDS fixes - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES interface - GPUVM fixes - PCIE DPM switching fixes for vega20 - Vega10 uclk DPM regression fix - DC Freesync fixes - DC ABM fixes - Various DC cleanups Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190208210214.27666-1-alexander.deucher@amd.com
2 parents 5ea3998 + 0461221 commit f4bc54b

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51 files changed

+1161
-486
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -214,6 +214,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs
214214
case AMDGPU_CHUNK_ID_DEPENDENCIES:
215215
case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
216216
case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
217+
case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
217218
break;
218219

219220
default:
@@ -1090,6 +1091,15 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
10901091

10911092
fence = amdgpu_ctx_get_fence(ctx, entity,
10921093
deps[i].handle);
1094+
1095+
if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
1096+
struct drm_sched_fence *s_fence = to_drm_sched_fence(fence);
1097+
struct dma_fence *old = fence;
1098+
1099+
fence = dma_fence_get(&s_fence->scheduled);
1100+
dma_fence_put(old);
1101+
}
1102+
10931103
if (IS_ERR(fence)) {
10941104
r = PTR_ERR(fence);
10951105
amdgpu_ctx_put(ctx);
@@ -1177,7 +1187,8 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
11771187

11781188
chunk = &p->chunks[i];
11791189

1180-
if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
1190+
if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES ||
1191+
chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
11811192
r = amdgpu_cs_process_fence_dep(p, chunk);
11821193
if (r)
11831194
return r;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 46 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -3618,6 +3618,38 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
36183618
return r;
36193619
}
36203620

3621+
static void amdgpu_device_get_min_pci_speed_width(struct amdgpu_device *adev,
3622+
enum pci_bus_speed *speed,
3623+
enum pcie_link_width *width)
3624+
{
3625+
struct pci_dev *pdev = adev->pdev;
3626+
enum pci_bus_speed cur_speed;
3627+
enum pcie_link_width cur_width;
3628+
3629+
*speed = PCI_SPEED_UNKNOWN;
3630+
*width = PCIE_LNK_WIDTH_UNKNOWN;
3631+
3632+
while (pdev) {
3633+
cur_speed = pcie_get_speed_cap(pdev);
3634+
cur_width = pcie_get_width_cap(pdev);
3635+
3636+
if (cur_speed != PCI_SPEED_UNKNOWN) {
3637+
if (*speed == PCI_SPEED_UNKNOWN)
3638+
*speed = cur_speed;
3639+
else if (cur_speed < *speed)
3640+
*speed = cur_speed;
3641+
}
3642+
3643+
if (cur_width != PCIE_LNK_WIDTH_UNKNOWN) {
3644+
if (*width == PCIE_LNK_WIDTH_UNKNOWN)
3645+
*width = cur_width;
3646+
else if (cur_width < *width)
3647+
*width = cur_width;
3648+
}
3649+
pdev = pci_upstream_bridge(pdev);
3650+
}
3651+
}
3652+
36213653
/**
36223654
* amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
36233655
*
@@ -3630,8 +3662,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
36303662
static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
36313663
{
36323664
struct pci_dev *pdev;
3633-
enum pci_bus_speed speed_cap;
3634-
enum pcie_link_width link_width;
3665+
enum pci_bus_speed speed_cap, platform_speed_cap;
3666+
enum pcie_link_width platform_link_width;
36353667

36363668
if (amdgpu_pcie_gen_cap)
36373669
adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
@@ -3648,6 +3680,12 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
36483680
return;
36493681
}
36503682

3683+
if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
3684+
return;
3685+
3686+
amdgpu_device_get_min_pci_speed_width(adev, &platform_speed_cap,
3687+
&platform_link_width);
3688+
36513689
if (adev->pm.pcie_gen_mask == 0) {
36523690
/* asic caps */
36533691
pdev = adev->pdev;
@@ -3673,22 +3711,20 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
36733711
adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
36743712
}
36753713
/* platform caps */
3676-
pdev = adev->ddev->pdev->bus->self;
3677-
speed_cap = pcie_get_speed_cap(pdev);
3678-
if (speed_cap == PCI_SPEED_UNKNOWN) {
3714+
if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
36793715
adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
36803716
CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
36813717
} else {
3682-
if (speed_cap == PCIE_SPEED_16_0GT)
3718+
if (platform_speed_cap == PCIE_SPEED_16_0GT)
36833719
adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
36843720
CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
36853721
CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
36863722
CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
3687-
else if (speed_cap == PCIE_SPEED_8_0GT)
3723+
else if (platform_speed_cap == PCIE_SPEED_8_0GT)
36883724
adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
36893725
CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
36903726
CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
3691-
else if (speed_cap == PCIE_SPEED_5_0GT)
3727+
else if (platform_speed_cap == PCIE_SPEED_5_0GT)
36923728
adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
36933729
CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
36943730
else
@@ -3697,12 +3733,10 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
36973733
}
36983734
}
36993735
if (adev->pm.pcie_mlw_mask == 0) {
3700-
pdev = adev->ddev->pdev->bus->self;
3701-
link_width = pcie_get_width_cap(pdev);
3702-
if (link_width == PCIE_LNK_WIDTH_UNKNOWN) {
3736+
if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
37033737
adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
37043738
} else {
3705-
switch (link_width) {
3739+
switch (platform_link_width) {
37063740
case PCIE_LNK_X32:
37073741
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
37083742
CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -71,9 +71,11 @@
7171
* - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
7272
* - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
7373
* - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
74+
* - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
75+
* - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
7476
*/
7577
#define KMS_DRIVER_MAJOR 3
76-
#define KMS_DRIVER_MINOR 27
78+
#define KMS_DRIVER_MINOR 29
7779
#define KMS_DRIVER_PATCHLEVEL 0
7880

7981
int amdgpu_vram_limit = 0;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,8 @@ struct amdgpu_gds {
3737
struct amdgpu_gds_asic_info mem;
3838
struct amdgpu_gds_asic_info gws;
3939
struct amdgpu_gds_asic_info oa;
40+
uint32_t gds_compute_max_wave_id;
41+
4042
/* At present, GDS, GWS and OA resources for gfx (graphics)
4143
* is always pre-allocated and available for graphics operation.
4244
* Such resource is shared between all gfx clients.

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -54,10 +54,6 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
5454

5555
memset(&bp, 0, sizeof(bp));
5656
*obj = NULL;
57-
/* At least align on page size */
58-
if (alignment < PAGE_SIZE) {
59-
alignment = PAGE_SIZE;
60-
}
6157

6258
bp.size = size;
6359
bp.byte_align = alignment;
@@ -244,9 +240,6 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
244240
return -EINVAL;
245241
}
246242
flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
247-
/* GDS allocations must be DW aligned */
248-
if (args->in.domains & AMDGPU_GEM_DOMAIN_GDS)
249-
size = ALIGN(size, 4);
250243
}
251244

252245
if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {

‎drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -426,12 +426,20 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
426426
size_t acc_size;
427427
int r;
428428

429-
page_align = roundup(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
430-
if (bp->domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS |
431-
AMDGPU_GEM_DOMAIN_OA))
429+
/* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
430+
if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
431+
/* GWS and OA don't need any alignment. */
432+
page_align = bp->byte_align;
432433
size <<= PAGE_SHIFT;
433-
else
434+
} else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
435+
/* Both size and alignment must be a multiple of 4. */
436+
page_align = ALIGN(bp->byte_align, 4);
437+
size = ALIGN(size, 4) << PAGE_SHIFT;
438+
} else {
439+
/* Memory should be aligned at least to a page size. */
440+
page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
434441
size = ALIGN(size, PAGE_SIZE);
442+
}
435443

436444
if (!amdgpu_bo_validate_size(adev, size, bp->domain))
437445
return -ENOMEM;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1756,7 +1756,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
17561756
}
17571757

17581758
r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1759-
PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1759+
4, AMDGPU_GEM_DOMAIN_GDS,
17601760
&adev->gds.gds_gfx_bo, NULL, NULL);
17611761
if (r)
17621762
return r;
@@ -1769,7 +1769,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
17691769
}
17701770

17711771
r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1772-
PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1772+
1, AMDGPU_GEM_DOMAIN_GWS,
17731773
&adev->gds.gws_gfx_bo, NULL, NULL);
17741774
if (r)
17751775
return r;
@@ -1782,7 +1782,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
17821782
}
17831783

17841784
r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1785-
PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1785+
1, AMDGPU_GEM_DOMAIN_OA,
17861786
&adev->gds.oa_gfx_bo, NULL, NULL);
17871787
if (r)
17881788
return r;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

Lines changed: 16 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -107,14 +107,6 @@ struct amdgpu_pte_update_params {
107107
* DMA addresses to use for mapping, used during VM update by CPU
108108
*/
109109
dma_addr_t *pages_addr;
110-
111-
/**
112-
* @kptr:
113-
*
114-
* Kernel pointer of PD/PT BO that needs to be updated,
115-
* used during VM update by CPU
116-
*/
117-
void *kptr;
118110
};
119111

120112
/**
@@ -1789,13 +1781,20 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
17891781
if (pages_addr)
17901782
params.src = ~0;
17911783

1792-
/* Wait for PT BOs to be free. PTs share the same resv. object
1784+
/* Wait for PT BOs to be idle. PTs share the same resv. object
17931785
* as the root PD BO
17941786
*/
17951787
r = amdgpu_vm_wait_pd(adev, vm, owner);
17961788
if (unlikely(r))
17971789
return r;
17981790

1791+
/* Wait for any BO move to be completed */
1792+
if (exclusive) {
1793+
r = dma_fence_wait(exclusive, true);
1794+
if (unlikely(r))
1795+
return r;
1796+
}
1797+
17991798
params.func = amdgpu_vm_cpu_set_ptes;
18001799
params.pages_addr = pages_addr;
18011800
return amdgpu_vm_update_ptes(&params, start, last + 1,
@@ -1809,13 +1808,12 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
18091808
/*
18101809
* reserve space for two commands every (1 << BLOCK_SIZE)
18111810
* entries or 2k dwords (whatever is smaller)
1812-
*
1813-
* The second command is for the shadow pagetables.
18141811
*/
1812+
ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1);
1813+
1814+
/* The second command is for the shadow pagetables. */
18151815
if (vm->root.base.bo->shadow)
1816-
ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2;
1817-
else
1818-
ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1);
1816+
ncmds *= 2;
18191817

18201818
/* padding, etc. */
18211819
ndw = 64;
@@ -1834,10 +1832,11 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
18341832
ndw += ncmds * 10;
18351833

18361834
/* extra commands for begin/end fragments */
1835+
ncmds = 2 * adev->vm_manager.fragment_size;
18371836
if (vm->root.base.bo->shadow)
1838-
ndw += 2 * 10 * adev->vm_manager.fragment_size * 2;
1839-
else
1840-
ndw += 2 * 10 * adev->vm_manager.fragment_size;
1837+
ncmds *= 2;
1838+
1839+
ndw += 10 * ncmds;
18411840

18421841
params.func = amdgpu_vm_do_set_ptes;
18431842
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,7 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
125125
if (!hive) {
126126
ret = -EINVAL;
127127
dev_err(adev->dev,
128-
"XGMI: node 0x%llx, can not matech hive 0x%llx in the hive list.\n",
128+
"XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n",
129129
adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id);
130130
goto exit;
131131
}

‎drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

Lines changed: 18 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2264,6 +2264,22 @@ static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
22642264
unsigned vmid = AMDGPU_JOB_GET_VMID(job);
22652265
u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
22662266

2267+
/* Currently, there is a high possibility to get wave ID mismatch
2268+
* between ME and GDS, leading to a hw deadlock, because ME generates
2269+
* different wave IDs than the GDS expects. This situation happens
2270+
* randomly when at least 5 compute pipes use GDS ordered append.
2271+
* The wave IDs generated by ME are also wrong after suspend/resume.
2272+
* Those are probably bugs somewhere else in the kernel driver.
2273+
*
2274+
* Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
2275+
* GDS to 0 for this ring (me/pipe).
2276+
*/
2277+
if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
2278+
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2279+
amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
2280+
amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
2281+
}
2282+
22672283
amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
22682284
amdgpu_ring_write(ring,
22692285
#ifdef __BIG_ENDIAN
@@ -5000,7 +5016,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
50005016
7 + /* gfx_v7_0_ring_emit_pipeline_sync */
50015017
CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */
50025018
7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5003-
.emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */
5019+
.emit_ib_size = 7, /* gfx_v7_0_ring_emit_ib_compute */
50045020
.emit_ib = gfx_v7_0_ring_emit_ib_compute,
50055021
.emit_fence = gfx_v7_0_ring_emit_fence_compute,
50065022
.emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
@@ -5057,6 +5073,7 @@ static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
50575073
adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
50585074
adev->gds.gws.total_size = 64;
50595075
adev->gds.oa.total_size = 16;
5076+
adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
50605077

50615078
if (adev->gds.mem.total_size == 64 * 1024) {
50625079
adev->gds.mem.gfx_partition_size = 4096;

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