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Merge tag 'irqdomain-for-linus' of git://git.secretlab.ca/git/linux-2.6
Pull irq_domain support for all architectures from Grant Likely: "Generialize powerpc's irq_host as irq_domain This branch takes the PowerPC irq_host infrastructure (reverse mapping from Linux IRQ numbers to hardware irq numbering), generalizes it, renames it to irq_domain, and makes it available to all architectures. Originally the plan has been to create an all-new irq_domain implementation which addresses some of the powerpc shortcomings such as not handling 1:1 mappings well, but doing that proved to be far more difficult and invasive than generalizing the working code and refactoring it in-place. So, this branch rips out the 'new' irq_domain and replaces it with the modified powerpc version (in a fully bisectable way of course). It converts all users over to the new API and makes irq_domain selectable on any architecture. No architecture is forced to enable irq_domain, but the infrastructure is required for doing OpenFirmware style irq translations. It will even work on SPARC even though SPARC has it's own mechanism for translating irqs at boot time. MIPS, microblaze, embedded x86 and c6x are converted too. The resulting irq_domain code is probably still too verbose and can be optimized more, but that can be done incrementally and is a task for follow-on patches." * tag 'irqdomain-for-linus' of git://git.secretlab.ca/git/linux-2.6: (31 commits) dt: fix twl4030 for non-dt compile on x86 mfd: twl-core: Add IRQ_DOMAIN dependency devicetree: Add empty of_platform_populate() for !CONFIG_OF_ADDRESS (sparc) irq_domain: Centralize definition of irq_dispose_mapping() irq_domain/mips: Allow irq_domain on MIPS irq_domain/x86: Convert x86 (embedded) to use common irq_domain ppc-6xx: fix build failure in flipper-pic.c and hlwd-pic.c irq_domain/microblaze: Convert microblaze to use irq_domains irq_domain/powerpc: Replace custom xlate functions with library functions irq_domain/powerpc: constify irq_domain_ops irq_domain/c6x: Use library of xlate functions irq_domain/c6x: constify irq_domain structures irq_domain/c6x: Convert c6x to use generic irq_domain support. irq_domain: constify irq_domain_ops irq_domain: Create common xlate functions that device drivers can use irq_domain: Remove irq_domain_add_simple() irq_domain: Remove 'new' irq_domain in favour of the ppc one mfd: twl-core.c: Fix the number of interrupts managed by twl4030 of/address: add empty static inlines for !CONFIG_OF irq_domain: Add support for base irq and hwirq in legacy mappings ...
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‎Documentation/IRQ-domain.txt

Lines changed: 117 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,117 @@
1+
irq_domain interrupt number mapping library
2+
3+
The current design of the Linux kernel uses a single large number
4+
space where each separate IRQ source is assigned a different number.
5+
This is simple when there is only one interrupt controller, but in
6+
systems with multiple interrupt controllers the kernel must ensure
7+
that each one gets assigned non-overlapping allocations of Linux
8+
IRQ numbers.
9+
10+
The irq_alloc_desc*() and irq_free_desc*() APIs provide allocation of
11+
irq numbers, but they don't provide any support for reverse mapping of
12+
the controller-local IRQ (hwirq) number into the Linux IRQ number
13+
space.
14+
15+
The irq_domain library adds mapping between hwirq and IRQ numbers on
16+
top of the irq_alloc_desc*() API. An irq_domain to manage mapping is
17+
preferred over interrupt controller drivers open coding their own
18+
reverse mapping scheme.
19+
20+
irq_domain also implements translation from Device Tree interrupt
21+
specifiers to hwirq numbers, and can be easily extended to support
22+
other IRQ topology data sources.
23+
24+
=== irq_domain usage ===
25+
An interrupt controller driver creates and registers an irq_domain by
26+
calling one of the irq_domain_add_*() functions (each mapping method
27+
has a different allocator function, more on that later). The function
28+
will return a pointer to the irq_domain on success. The caller must
29+
provide the allocator function with an irq_domain_ops structure with
30+
the .map callback populated as a minimum.
31+
32+
In most cases, the irq_domain will begin empty without any mappings
33+
between hwirq and IRQ numbers. Mappings are added to the irq_domain
34+
by calling irq_create_mapping() which accepts the irq_domain and a
35+
hwirq number as arguments. If a mapping for the hwirq doesn't already
36+
exist then it will allocate a new Linux irq_desc, associate it with
37+
the hwirq, and call the .map() callback so the driver can perform any
38+
required hardware setup.
39+
40+
When an interrupt is received, irq_find_mapping() function should
41+
be used to find the Linux IRQ number from the hwirq number.
42+
43+
If the driver has the Linux IRQ number or the irq_data pointer, and
44+
needs to know the associated hwirq number (such as in the irq_chip
45+
callbacks) then it can be directly obtained from irq_data->hwirq.
46+
47+
=== Types of irq_domain mappings ===
48+
There are several mechanisms available for reverse mapping from hwirq
49+
to Linux irq, and each mechanism uses a different allocation function.
50+
Which reverse map type should be used depends on the use case. Each
51+
of the reverse map types are described below:
52+
53+
==== Linear ====
54+
irq_domain_add_linear()
55+
56+
The linear reverse map maintains a fixed size table indexed by the
57+
hwirq number. When a hwirq is mapped, an irq_desc is allocated for
58+
the hwirq, and the IRQ number is stored in the table.
59+
60+
The Linear map is a good choice when the maximum number of hwirqs is
61+
fixed and a relatively small number (~ < 256). The advantages of this
62+
map are fixed time lookup for IRQ numbers, and irq_descs are only
63+
allocated for in-use IRQs. The disadvantage is that the table must be
64+
as large as the largest possible hwirq number.
65+
66+
The majority of drivers should use the linear map.
67+
68+
==== Tree ====
69+
irq_domain_add_tree()
70+
71+
The irq_domain maintains a radix tree map from hwirq numbers to Linux
72+
IRQs. When an hwirq is mapped, an irq_desc is allocated and the
73+
hwirq is used as the lookup key for the radix tree.
74+
75+
The tree map is a good choice if the hwirq number can be very large
76+
since it doesn't need to allocate a table as large as the largest
77+
hwirq number. The disadvantage is that hwirq to IRQ number lookup is
78+
dependent on how many entries are in the table.
79+
80+
Very few drivers should need this mapping. At the moment, powerpc
81+
iseries is the only user.
82+
83+
==== No Map ===-
84+
irq_domain_add_nomap()
85+
86+
The No Map mapping is to be used when the hwirq number is
87+
programmable in the hardware. In this case it is best to program the
88+
Linux IRQ number into the hardware itself so that no mapping is
89+
required. Calling irq_create_direct_mapping() will allocate a Linux
90+
IRQ number and call the .map() callback so that driver can program the
91+
Linux IRQ number into the hardware.
92+
93+
Most drivers cannot use this mapping.
94+
95+
==== Legacy ====
96+
irq_domain_add_legacy()
97+
irq_domain_add_legacy_isa()
98+
99+
The Legacy mapping is a special case for drivers that already have a
100+
range of irq_descs allocated for the hwirqs. It is used when the
101+
driver cannot be immediately converted to use the linear mapping. For
102+
example, many embedded system board support files use a set of #defines
103+
for IRQ numbers that are passed to struct device registrations. In that
104+
case the Linux IRQ numbers cannot be dynamically assigned and the legacy
105+
mapping should be used.
106+
107+
The legacy map assumes a contiguous range of IRQ numbers has already
108+
been allocated for the controller and that the IRQ number can be
109+
calculated by adding a fixed offset to the hwirq number, and
110+
visa-versa. The disadvantage is that it requires the interrupt
111+
controller to manage IRQ allocations and it requires an irq_desc to be
112+
allocated for every hwirq, even if it is unused.
113+
114+
The legacy map should only be used if fixed IRQ mappings must be
115+
supported. For example, ISA controllers would use the legacy map for
116+
mapping Linux IRQs 0-15 so that existing ISA drivers get the correct IRQ
117+
numbers.

‎MAINTAINERS

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3666,6 +3666,15 @@ S: Maintained
36663666
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
36673667
F: kernel/irq/
36683668

3669+
IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY)
3670+
M: Benjamin Herrenschmidt <benh@kernel.crashing.org>
3671+
M: Grant Likely <grant.likely@secretlab.ca>
3672+
T: git git://git.secretlab.ca/git/linux-2.6.git irqdomain/next
3673+
S: Maintained
3674+
F: Documentation/IRQ-domain.txt
3675+
F: include/linux/irqdomain.h
3676+
F: kernel/irq/irqdomain.c
3677+
36693678
ISAPNP
36703679
M: Jaroslav Kysela <perex@perex.cz>
36713680
S: Maintained

‎arch/arm/common/gic.c

Lines changed: 42 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,6 @@ union gic_base {
5151
};
5252

5353
struct gic_chip_data {
54-
unsigned int irq_offset;
5554
union gic_base dist_base;
5655
union gic_base cpu_base;
5756
#ifdef CONFIG_CPU_PM
@@ -61,9 +60,7 @@ struct gic_chip_data {
6160
u32 __percpu *saved_ppi_enable;
6261
u32 __percpu *saved_ppi_conf;
6362
#endif
64-
#ifdef CONFIG_IRQ_DOMAIN
65-
struct irq_domain domain;
66-
#endif
63+
struct irq_domain *domain;
6764
unsigned int gic_irqs;
6865
#ifdef CONFIG_GIC_NON_BANKED
6966
void __iomem *(*get_base)(union gic_base *);
@@ -282,7 +279,7 @@ asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
282279
irqnr = irqstat & ~0x1c00;
283280

284281
if (likely(irqnr > 15 && irqnr < 1021)) {
285-
irqnr = irq_domain_to_irq(&gic->domain, irqnr);
282+
irqnr = irq_find_mapping(gic->domain, irqnr);
286283
handle_IRQ(irqnr, regs);
287284
continue;
288285
}
@@ -314,8 +311,8 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
314311
if (gic_irq == 1023)
315312
goto out;
316313

317-
cascade_irq = irq_domain_to_irq(&chip_data->domain, gic_irq);
318-
if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
314+
cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
315+
if (unlikely(gic_irq < 32 || gic_irq > 1020))
319316
do_bad_IRQ(cascade_irq, desc);
320317
else
321318
generic_handle_irq(cascade_irq);
@@ -348,10 +345,9 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
348345

349346
static void __init gic_dist_init(struct gic_chip_data *gic)
350347
{
351-
unsigned int i, irq;
348+
unsigned int i;
352349
u32 cpumask;
353350
unsigned int gic_irqs = gic->gic_irqs;
354-
struct irq_domain *domain = &gic->domain;
355351
void __iomem *base = gic_data_dist_base(gic);
356352
u32 cpu = cpu_logical_map(smp_processor_id());
357353

@@ -386,23 +382,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
386382
for (i = 32; i < gic_irqs; i += 32)
387383
writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
388384

389-
/*
390-
* Setup the Linux IRQ subsystem.
391-
*/
392-
irq_domain_for_each_irq(domain, i, irq) {
393-
if (i < 32) {
394-
irq_set_percpu_devid(irq);
395-
irq_set_chip_and_handler(irq, &gic_chip,
396-
handle_percpu_devid_irq);
397-
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
398-
} else {
399-
irq_set_chip_and_handler(irq, &gic_chip,
400-
handle_fasteoi_irq);
401-
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
402-
}
403-
irq_set_chip_data(irq, gic);
404-
}
405-
406385
writel_relaxed(1, base + GIC_DIST_CTRL);
407386
}
408387

@@ -618,11 +597,27 @@ static void __init gic_pm_init(struct gic_chip_data *gic)
618597
}
619598
#endif
620599

621-
#ifdef CONFIG_OF
622-
static int gic_irq_domain_dt_translate(struct irq_domain *d,
623-
struct device_node *controller,
624-
const u32 *intspec, unsigned int intsize,
625-
unsigned long *out_hwirq, unsigned int *out_type)
600+
static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
601+
irq_hw_number_t hw)
602+
{
603+
if (hw < 32) {
604+
irq_set_percpu_devid(irq);
605+
irq_set_chip_and_handler(irq, &gic_chip,
606+
handle_percpu_devid_irq);
607+
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
608+
} else {
609+
irq_set_chip_and_handler(irq, &gic_chip,
610+
handle_fasteoi_irq);
611+
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
612+
}
613+
irq_set_chip_data(irq, d->host_data);
614+
return 0;
615+
}
616+
617+
static int gic_irq_domain_xlate(struct irq_domain *d,
618+
struct device_node *controller,
619+
const u32 *intspec, unsigned int intsize,
620+
unsigned long *out_hwirq, unsigned int *out_type)
626621
{
627622
if (d->of_node != controller)
628623
return -EINVAL;
@@ -639,26 +634,23 @@ static int gic_irq_domain_dt_translate(struct irq_domain *d,
639634
*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
640635
return 0;
641636
}
642-
#endif
643637

644638
const struct irq_domain_ops gic_irq_domain_ops = {
645-
#ifdef CONFIG_OF
646-
.dt_translate = gic_irq_domain_dt_translate,
647-
#endif
639+
.map = gic_irq_domain_map,
640+
.xlate = gic_irq_domain_xlate,
648641
};
649642

650643
void __init gic_init_bases(unsigned int gic_nr, int irq_start,
651644
void __iomem *dist_base, void __iomem *cpu_base,
652-
u32 percpu_offset)
645+
u32 percpu_offset, struct device_node *node)
653646
{
647+
irq_hw_number_t hwirq_base;
654648
struct gic_chip_data *gic;
655-
struct irq_domain *domain;
656-
int gic_irqs;
649+
int gic_irqs, irq_base;
657650

658651
BUG_ON(gic_nr >= MAX_GIC_NR);
659652

660653
gic = &gic_data[gic_nr];
661-
domain = &gic->domain;
662654
#ifdef CONFIG_GIC_NON_BANKED
663655
if (percpu_offset) { /* Frankein-GIC without banked registers... */
664656
unsigned int cpu;
@@ -694,10 +686,10 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
694686
* For primary GICs, skip over SGIs.
695687
* For secondary GICs, skip over PPIs, too.
696688
*/
697-
domain->hwirq_base = 32;
689+
hwirq_base = 32;
698690
if (gic_nr == 0) {
699691
if ((irq_start & 31) > 0) {
700-
domain->hwirq_base = 16;
692+
hwirq_base = 16;
701693
if (irq_start != -1)
702694
irq_start = (irq_start & ~31) + 16;
703695
}
@@ -713,17 +705,17 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
713705
gic_irqs = 1020;
714706
gic->gic_irqs = gic_irqs;
715707

716-
domain->nr_irq = gic_irqs - domain->hwirq_base;
717-
domain->irq_base = irq_alloc_descs(irq_start, 16, domain->nr_irq,
718-
numa_node_id());
719-
if (IS_ERR_VALUE(domain->irq_base)) {
708+
gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
709+
irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
710+
if (IS_ERR_VALUE(irq_base)) {
720711
WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
721712
irq_start);
722-
domain->irq_base = irq_start;
713+
irq_base = irq_start;
723714
}
724-
domain->priv = gic;
725-
domain->ops = &gic_irq_domain_ops;
726-
irq_domain_add(domain);
715+
gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
716+
hwirq_base, &gic_irq_domain_ops, gic);
717+
if (WARN_ON(!gic->domain))
718+
return;
727719

728720
gic_chip.flags |= gic_arch_extn.flags;
729721
gic_dist_init(gic);
@@ -768,7 +760,6 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
768760
void __iomem *dist_base;
769761
u32 percpu_offset;
770762
int irq;
771-
struct irq_domain *domain = &gic_data[gic_cnt].domain;
772763

773764
if (WARN_ON(!node))
774765
return -ENODEV;
@@ -782,9 +773,7 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
782773
if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
783774
percpu_offset = 0;
784775

785-
domain->of_node = of_node_get(node);
786-
787-
gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset);
776+
gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
788777

789778
if (parent) {
790779
irq = irq_of_parse_and_map(node, 0);

‎arch/arm/common/vic.c

Lines changed: 5 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ struct vic_device {
5656
u32 int_enable;
5757
u32 soft_int;
5858
u32 protect;
59-
struct irq_domain domain;
59+
struct irq_domain *domain;
6060
};
6161

6262
/* we cannot allocate memory when VICs are initially registered */
@@ -192,14 +192,8 @@ static void __init vic_register(void __iomem *base, unsigned int irq,
192192
v->resume_sources = resume_sources;
193193
v->irq = irq;
194194
vic_id++;
195-
196-
v->domain.irq_base = irq;
197-
v->domain.nr_irq = 32;
198-
#ifdef CONFIG_OF_IRQ
199-
v->domain.of_node = of_node_get(node);
200-
#endif /* CONFIG_OF */
201-
v->domain.ops = &irq_domain_simple_ops;
202-
irq_domain_add(&v->domain);
195+
v->domain = irq_domain_add_legacy(node, 32, irq, 0,
196+
&irq_domain_simple_ops, v);
203197
}
204198

205199
static void vic_ack_irq(struct irq_data *d)
@@ -348,7 +342,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
348342
vic_register(base, irq_start, 0, node);
349343
}
350344

351-
static void __init __vic_init(void __iomem *base, unsigned int irq_start,
345+
void __init __vic_init(void __iomem *base, unsigned int irq_start,
352346
u32 vic_sources, u32 resume_sources,
353347
struct device_node *node)
354348
{
@@ -444,7 +438,7 @@ static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
444438
stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
445439
while (stat) {
446440
irq = ffs(stat) - 1;
447-
handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs);
441+
handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
448442
stat &= ~(1 << irq);
449443
handled = 1;
450444
}

‎arch/arm/include/asm/hardware/gic.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ struct device_node;
3939
extern struct irq_chip gic_arch_extn;
4040

4141
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
42-
u32 offset);
42+
u32 offset, struct device_node *);
4343
int gic_of_init(struct device_node *node, struct device_node *parent);
4444
void gic_secondary_init(unsigned int);
4545
void gic_handle_irq(struct pt_regs *regs);
@@ -49,7 +49,7 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
4949
static inline void gic_init(unsigned int nr, int start,
5050
void __iomem *dist , void __iomem *cpu)
5151
{
52-
gic_init_bases(nr, start, dist, cpu, 0);
52+
gic_init_bases(nr, start, dist, cpu, 0, NULL);
5353
}
5454

5555
#endif

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