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Revert "[X86] Merge the FEATURE_64BIT and FEATURE_EM64T bits in X86TargetParser.def."
An accidental change snuck in here This reverts commit f1d290d.
1 parent f1d290d commit d92bf71

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4 files changed

+28
-30
lines changed

4 files changed

+28
-30
lines changed

‎llvm/include/llvm/Support/X86TargetParser.def

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -184,6 +184,10 @@ X86_FEATURE (CLWB, "clwb")
184184
X86_FEATURE (CLZERO, "clzero")
185185
X86_FEATURE (CMPXCHG16B, "cx16")
186186
X86_FEATURE (CMPXCHG8B, "cx8")
187+
// FIXME: Merge with 64BIT? Currently separate to be used to tell if CPU is
188+
// valid for 64-bit mode, but has empty string so it doesn't get added to
189+
// target attributes in IR.
190+
X86_FEATURE (EM64T, "")
187191
X86_FEATURE (ENQCMD, "enqcmd")
188192
X86_FEATURE (F16C, "f16c")
189193
X86_FEATURE (FSGSBASE, "fsgsbase")

‎llvm/lib/Analysis/InstructionSimplify.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4117,6 +4117,11 @@ static Value *SimplifySelectInst(Value *Cond, Value *TrueVal, Value *FalseVal,
41174117
if (TrueVal == FalseVal)
41184118
return TrueVal;
41194119

4120+
if (isa<UndefValue>(TrueVal)) // select ?, undef, X -> X
4121+
return FalseVal;
4122+
if (isa<UndefValue>(FalseVal)) // select ?, X, undef -> X
4123+
return TrueVal;
4124+
41204125
// Deal with partial undef vector constants: select ?, VecC, VecC' --> VecC''
41214126
Constant *TrueC, *FalseC;
41224127
if (TrueVal->getType()->isVectorTy() && match(TrueVal, m_Constant(TrueC)) &&

‎llvm/lib/Support/Host.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -868,7 +868,7 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
868868
}
869869
break;
870870
}
871-
if (testFeature(X86::FEATURE_64BIT)) {
871+
if (testFeature(X86::FEATURE_EM64T)) {
872872
*Type = X86::INTEL_CORE2; // "core2"
873873
*Subtype = X86::INTEL_CORE2_65;
874874
break;
@@ -894,7 +894,7 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
894894
}
895895
break;
896896
case 15: {
897-
if (testFeature(X86::FEATURE_64BIT)) {
897+
if (testFeature(X86::FEATURE_EM64T)) {
898898
*Type = X86::INTEL_NOCONA;
899899
break;
900900
}
@@ -1140,7 +1140,7 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
11401140
setFeature(X86::FEATURE_FMA4);
11411141

11421142
if (HasExtLeaf1 && ((EDX >> 29) & 1))
1143-
setFeature(X86::FEATURE_64BIT);
1143+
setFeature(X86::FEATURE_EM64T);
11441144
}
11451145

11461146
StringRef sys::getHostCPUName() {

‎llvm/lib/Support/X86TargetParser.cpp

Lines changed: 16 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -48,14 +48,6 @@ class FeatureBitset {
4848
return (Bits[I / 32] & Mask) != 0;
4949
}
5050

51-
constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
52-
for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
53-
uint32_t NewBits = Bits[I] & RHS.Bits[I];
54-
Bits[I] = NewBits;
55-
}
56-
return *this;
57-
}
58-
5951
constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
6052
for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
6153
uint32_t NewBits = Bits[I] | RHS.Bits[I];
@@ -65,14 +57,16 @@ class FeatureBitset {
6557
}
6658

6759
constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
68-
FeatureBitset Result = *this;
69-
Result &= RHS;
60+
FeatureBitset Result;
61+
for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
62+
Result.Bits[I] = Bits[I] & RHS.Bits[I];
7063
return Result;
7164
}
7265

7366
constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
74-
FeatureBitset Result = *this;
75-
Result |= RHS;
67+
FeatureBitset Result;
68+
for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
69+
Result.Bits[I] = Bits[I] | RHS.Bits[I];
7670
return Result;
7771
}
7872

@@ -117,10 +111,10 @@ static constexpr FeatureBitset FeaturesPentium4 =
117111
static constexpr FeatureBitset FeaturesPrescott =
118112
FeaturesPentium4 | FeatureSSE3;
119113
static constexpr FeatureBitset FeaturesNocona =
120-
FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
114+
FeaturesPrescott | FeatureEM64T | FeatureCMPXCHG16B;
121115

122116
// Basic 64-bit capable CPU.
123-
static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
117+
static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | FeatureEM64T;
124118

125119
// Intel Core CPUs
126120
static constexpr FeatureBitset FeaturesCore2 =
@@ -207,15 +201,15 @@ static constexpr FeatureBitset FeaturesAthlon =
207201
static constexpr FeatureBitset FeaturesAthlonXP =
208202
FeaturesAthlon | FeatureFXSR | FeatureSSE;
209203
static constexpr FeatureBitset FeaturesK8 =
210-
FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
204+
FeaturesAthlonXP | FeatureSSE2 | FeatureEM64T;
211205
static constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
212206
static constexpr FeatureBitset FeaturesAMDFAM10 =
213207
FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
214208
FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
215209

216210
// Bobcat architecture processors.
217211
static constexpr FeatureBitset FeaturesBTVER1 =
218-
FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
212+
FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureEM64T |
219213
FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
220214
FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
221215
FeatureSAHF;
@@ -226,7 +220,7 @@ static constexpr FeatureBitset FeaturesBTVER2 =
226220
// AMD Bulldozer architecture processors.
227221
static constexpr FeatureBitset FeaturesBDVER1 =
228222
FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
229-
FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP |
223+
FeatureCMPXCHG16B | FeatureEM64T | FeatureFMA4 | FeatureFXSR | FeatureLWP |
230224
FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW |
231225
FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 |
232226
FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE;
@@ -242,7 +236,7 @@ static constexpr FeatureBitset FeaturesBDVER4 =
242236
static constexpr FeatureBitset FeaturesZNVER1 =
243237
FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
244238
FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
245-
FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C |
239+
FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureEM64T | FeatureF16C |
246240
FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX |
247241
FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
248242
FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
@@ -369,7 +363,7 @@ static constexpr ProcInfo Processors[] = {
369363

370364
X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
371365
for (const auto &P : Processors)
372-
if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
366+
if (P.Name == CPU && (P.Features[FEATURE_EM64T] || !Only64Bit))
373367
return P.Kind;
374368

375369
return CK_None;
@@ -378,7 +372,7 @@ X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
378372
void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
379373
bool Only64Bit) {
380374
for (const auto &P : Processors)
381-
if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
375+
if (!P.Name.empty() && (P.Features[FEATURE_EM64T] || !Only64Bit))
382376
Values.emplace_back(P.Name);
383377
}
384378

@@ -407,6 +401,7 @@ static constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
407401
static constexpr FeatureBitset ImpliedFeaturesCMOV = {};
408402
static constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
409403
static constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
404+
static constexpr FeatureBitset ImpliedFeaturesEM64T = {};
410405
static constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
411406
static constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
412407
static constexpr FeatureBitset ImpliedFeaturesFXSR = {};
@@ -533,14 +528,8 @@ void llvm::X86::getFeaturesForCPU(StringRef CPU,
533528
[&](const ProcInfo &P) { return P.Name == CPU; });
534529
assert(I != std::end(Processors) && "Processor not found!");
535530

536-
FeatureBitset Bits = I->Features;
537-
538-
// Remove the 64-bit feature which we only use to validate if a CPU can
539-
// be used with 64-bit mode.
540-
Bits &= ~Feature64BIT;
541-
542531
// Add the string version of all set bits.
543-
getFeatureBitsAsStrings(Bits, EnabledFeatures);
532+
getFeatureBitsAsStrings(I->Features, EnabledFeatures);
544533
}
545534

546535
// For each feature that is (transitively) implied by this feature, set it.

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