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[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)
recreate this patch from #153894 It seems ISel sliently ignore the `i64 = zext i16` with a chained `reg_sequence` pattern and thus this is causing a selection failure in hip test. Recreate a new patch with an alternative pattern, and added a ll test global-extload-gfx11plus.ll
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‎llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 24 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3078,6 +3078,8 @@ def : GCNPat<
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}
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} // AddedComplexity = 1
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foreach p = [NotHasTrue16BitInsts, UseFakeTrue16Insts] in
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let True16Predicate = p in {
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def : GCNPat<
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(i32 (DivergentUnaryFrag<zext> i16:$src)),
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(V_AND_B32_e64 (S_MOV_B32 (i32 0xffff)), $src)
@@ -3092,7 +3094,28 @@ def : GCNPat<
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def : GCNPat<
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(i32 (zext (i16 (bitconvert fp16_zeros_high_16bits:$src)))),
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(COPY VSrc_b16:$src)>;
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(COPY VSrc_b16:$src)
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>;
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}
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let True16Predicate = UseRealTrue16Insts in {
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def : GCNPat<
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(i32 (DivergentUnaryFrag<zext> i16:$src)),
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(REG_SEQUENCE VGPR_32, VGPR_16:$src, lo16, (V_MOV_B16_t16_e64 0, (i16 0), 0), hi16)
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>;
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def : GCNPat<
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(i64 (DivergentUnaryFrag<zext> i16:$src)),
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(REG_SEQUENCE VReg_64,
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(INSERT_SUBREG (i32 (V_MOV_B32_e32 (i32 0))), VGPR_16:$src, lo16), sub0,
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(S_MOV_B32 (i32 0)), sub1)
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>;
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def : GCNPat<
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(i32 (zext (i16 (bitconvert fp16_zeros_high_16bits:$src)))),
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(REG_SEQUENCE VGPR_32, VGPR_16:$src, lo16, (V_MOV_B16_t16_e64 0, (i16 0), 0), hi16)
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>;
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}
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def : GCNPat <
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(i32 (trunc i64:$a)),

‎llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -164,7 +164,7 @@ define zeroext i16 @v_mul_i16_zeroext(i16 zeroext %num, i16 zeroext %den) {
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; GFX11-TRUE16: ; %bb.0:
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; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
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; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0
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; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-FAKE16-LABEL: v_mul_i16_zeroext:

‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll

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‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll

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‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll

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‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll

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‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll

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‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll

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‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll

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‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll

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