llvm
diff --git a/‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Lines changed: 9 additions & 0 deletions b/‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Lines changed: 9 additions & 0 deletions
diff --git a/‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
Lines changed: 6 additions & 0 deletions b/‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
Lines changed: 6 additions & 0 deletions
@@ -4773,6 +4773,15 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
     return lowerVectorReduction(MI);
   case G_VAARG:
     return lowerVAArg(MI);
+  case G_ATOMICRMW_SUB: {
+    auto [Ret, RetLLT, Mem, MemLLT, Val, ValLLT] = MI.getFirst3RegLLTs();
+    MachineMemOperand *MMO = *MI.memoperands_begin();
+
+    auto VNeg = MIRBuilder.buildNeg(ValLLT, Val);
+    MIRBuilder.buildAtomicRMW(G_ATOMICRMW_ADD, Ret, Mem, VNeg, *MMO);
+    MI.eraseFromParent();
+    return Legalized;
+  }
   }
 }
 
 
@@ -700,6 +700,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
       .libcallFor(!ST.hasStdExtA(), {{s8, p0}, {s16, p0}, {s32, p0}, {s64, p0}})
       .clampScalar(0, sXLen, sXLen);
 
+  getActionDefinitionsBuilder(G_ATOMICRMW_SUB)
+      .libcallFor(!ST.hasStdExtA(), {{s8, p0}, {s16, p0}, {s32, p0}, {s64, p0}})
+      .clampScalar(0, sXLen, sXLen)
+      .lower();
+
   getLegacyLegalizerInfo().computeTables();
   verify(*ST.getInstrInfo());
 }
@@ -738,6 +743,7 @@ bool RISCVLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
     return true;
   }
   case Intrinsic::riscv_masked_atomicrmw_add:
+  case Intrinsic::riscv_masked_atomicrmw_sub:
     return true;
   }
 }
Original file line number	Diff line number	Diff line change
`@@ -700,6 +700,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)`
`700`	`700`	`.libcallFor(!ST.hasStdExtA(), {{s8, p0}, {s16, p0}, {s32, p0}, {s64, p0}})`
`701`	`701`	`.clampScalar(0, sXLen, sXLen);`
`702`	`702`
	`703`	`+ getActionDefinitionsBuilder(G_ATOMICRMW_SUB)`
	`704`	`+ .libcallFor(!ST.hasStdExtA(), {{s8, p0}, {s16, p0}, {s32, p0}, {s64, p0}})`
	`705`	`+ .clampScalar(0, sXLen, sXLen)`
	`706`	`+ .lower();`
	`707`	`+`
`703`	`708`	`getLegacyLegalizerInfo().computeTables();`
`704`	`709`	`verify(*ST.getInstrInfo());`
`705`	`710`	`}`
`@@ -738,6 +743,7 @@ bool RISCVLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,`
`738`	`743`	`return true;`
`739`	`744`	`}`
`740`	`745`	`case Intrinsic::riscv_masked_atomicrmw_add:`
	`746`	`+ case Intrinsic::riscv_masked_atomicrmw_sub:`
`741`	`747`	`return true;`
`742`	`748`	`}`
`743`	`749`	`}`