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[RISCV] Mark More Fatal Errors as Usage/Internal (#154876)
We have lots of uses of `report_fatal_error` in the backend, which will result in a crash and a backtrace. This API has been replaced with `reportFatalUsageError` and `reportFatalInternalError`, for which only the latter emits a stack trace. This tries to move the errors in RISCVISelLowering and RISCVRegisterInfo to the new APIs, to prevent some stack traces where we specificially do not support certain situations. Updates #124132
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9 files changed

+48
-46
lines changed

9 files changed

+48
-46
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 31 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -109,7 +109,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
109109

110110
switch (ABI) {
111111
default:
112-
report_fatal_error("Don't know how to lower this ABI");
112+
reportFatalUsageError("Don't know how to lower this ABI");
113113
case RISCVABI::ABI_ILP32:
114114
case RISCVABI::ABI_ILP32E:
115115
case RISCVABI::ABI_LP64E:
@@ -7305,7 +7305,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
73057305
SelectionDAG &DAG) const {
73067306
switch (Op.getOpcode()) {
73077307
default:
7308-
report_fatal_error("unimplemented operand");
7308+
reportFatalInternalError(
7309+
"Unimplemented RISCVTargetLowering::LowerOperation Case");
73097310
case ISD::PREFETCH:
73107311
return LowerPREFETCH(Op, Subtarget, DAG);
73117312
case ISD::ATOMIC_FENCE:
@@ -7503,7 +7504,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
75037504
// vscale as VLENB / 8.
75047505
static_assert(RISCV::RVVBitsPerBlock == 64, "Unexpected bits per block!");
75057506
if (Subtarget.getRealMinVLen() < RISCV::RVVBitsPerBlock)
7506-
report_fatal_error("Support for VLEN==32 is incomplete.");
7507+
reportFatalInternalError("Support for VLEN==32 is incomplete.");
75077508
// We assume VLENB is a multiple of 8. We manually choose the best shift
75087509
// here because SimplifyDemandedBits isn't always able to simplify it.
75097510
uint64_t Val = Op.getConstantOperandVal(0);
@@ -8516,7 +8517,7 @@ SDValue RISCVTargetLowering::emitFlushICache(SelectionDAG &DAG, SDValue InChain,
85168517
SDValue RISCVTargetLowering::lowerINIT_TRAMPOLINE(SDValue Op,
85178518
SelectionDAG &DAG) const {
85188519
if (!Subtarget.is64Bit())
8519-
llvm::report_fatal_error("Trampolines only implemented for RV64");
8520+
llvm::reportFatalUsageError("Trampolines only implemented for RV64");
85208521

85218522
// Create an MCCodeEmitter to encode instructions.
85228523
TargetLoweringObjectFile *TLO = getTargetMachine().getObjFileLowering();
@@ -8676,7 +8677,7 @@ SDValue RISCVTargetLowering::lowerINIT_TRAMPOLINE(SDValue Op,
86768677
SDValue RISCVTargetLowering::lowerADJUST_TRAMPOLINE(SDValue Op,
86778678
SelectionDAG &DAG) const {
86788679
if (!Subtarget.is64Bit())
8679-
llvm::report_fatal_error("Trampolines only implemented for RV64");
8680+
llvm::reportFatalUsageError("Trampolines only implemented for RV64");
86808681

86818682
return Op.getOperand(0);
86828683
}
@@ -8811,7 +8812,7 @@ SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
88118812

88128813
switch (getTargetMachine().getCodeModel()) {
88138814
default:
8814-
report_fatal_error("Unsupported code model for lowering");
8815+
reportFatalUsageError("Unsupported code model for lowering");
88158816
case CodeModel::Small: {
88168817
// Generate a sequence for accessing addresses within the first 2 GiB of
88178818
// address space. This generates the pattern (addi (lui %hi(sym)) %lo(sym)).
@@ -8989,7 +8990,7 @@ SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,
89898990

89908991
if (DAG.getMachineFunction().getFunction().getCallingConv() ==
89918992
CallingConv::GHC)
8992-
report_fatal_error("In GHC calling convention TLS is not supported");
8993+
reportFatalUsageError("In GHC calling convention TLS is not supported");
89938994

89948995
SDValue Addr;
89958996
switch (Model) {
@@ -10838,15 +10839,15 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
1083810839
if (!isValidEGW(4, Op.getSimpleValueType(), Subtarget) ||
1083910840
!isValidEGW(4, Op->getOperand(1).getSimpleValueType(), Subtarget) ||
1084010841
!isValidEGW(4, Op->getOperand(2).getSimpleValueType(), Subtarget))
10841-
report_fatal_error("EGW should be greater than or equal to 4 * SEW.");
10842+
reportFatalUsageError("EGW should be greater than or equal to 4 * SEW.");
1084210843
return Op;
1084310844
}
1084410845
// EGS * EEW >= 256 bits
1084510846
case Intrinsic::riscv_vsm3c:
1084610847
case Intrinsic::riscv_vsm3me: {
1084710848
if (!isValidEGW(8, Op.getSimpleValueType(), Subtarget) ||
1084810849
!isValidEGW(8, Op->getOperand(1).getSimpleValueType(), Subtarget))
10849-
report_fatal_error("EGW should be greater than or equal to 8 * SEW.");
10850+
reportFatalUsageError("EGW should be greater than or equal to 8 * SEW.");
1085010851
return Op;
1085110852
}
1085210853
// zvknha(SEW=32)/zvknhb(SEW=[32|64])
@@ -10855,11 +10856,11 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
1085510856
case Intrinsic::riscv_vsha2ms: {
1085610857
if (Op->getSimpleValueType(0).getScalarSizeInBits() == 64 &&
1085710858
!Subtarget.hasStdExtZvknhb())
10858-
report_fatal_error("SEW=64 needs Zvknhb to be enabled.");
10859+
reportFatalUsageError("SEW=64 needs Zvknhb to be enabled.");
1085910860
if (!isValidEGW(4, Op.getSimpleValueType(), Subtarget) ||
1086010861
!isValidEGW(4, Op->getOperand(1).getSimpleValueType(), Subtarget) ||
1086110862
!isValidEGW(4, Op->getOperand(2).getSimpleValueType(), Subtarget))
10862-
report_fatal_error("EGW should be greater than or equal to 4 * SEW.");
10863+
reportFatalUsageError("EGW should be greater than or equal to 4 * SEW.");
1086310864
return Op;
1086410865
}
1086510866
case Intrinsic::riscv_sf_vc_v_x:
@@ -22334,8 +22335,8 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
2233422335
case TargetOpcode::STACKMAP:
2233522336
case TargetOpcode::PATCHPOINT:
2233622337
if (!Subtarget.is64Bit())
22337-
report_fatal_error("STACKMAP, PATCHPOINT and STATEPOINT are only "
22338-
"supported on 64-bit targets");
22338+
reportFatalUsageError("STACKMAP, PATCHPOINT and STATEPOINT are only "
22339+
"supported on 64-bit targets");
2233922340
return emitPatchPoint(MI, BB);
2234022341
}
2234122342
}
@@ -22568,7 +22569,7 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
2256822569

2256922570
switch (CallConv) {
2257022571
default:
22571-
report_fatal_error("Unsupported calling convention");
22572+
reportFatalUsageError("Unsupported calling convention");
2257222573
case CallingConv::C:
2257322574
case CallingConv::Fast:
2257422575
case CallingConv::SPIR_KERNEL:
@@ -22592,17 +22593,17 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
2259222593
break;
2259322594
case CallingConv::GHC:
2259422595
if (Subtarget.hasStdExtE())
22595-
report_fatal_error("GHC calling convention is not supported on RVE!");
22596+
reportFatalUsageError("GHC calling convention is not supported on RVE!");
2259622597
if (!Subtarget.hasStdExtFOrZfinx() || !Subtarget.hasStdExtDOrZdinx())
22597-
report_fatal_error("GHC calling convention requires the (Zfinx/F) and "
22598-
"(Zdinx/D) instruction set extensions");
22598+
reportFatalUsageError("GHC calling convention requires the (Zfinx/F) and "
22599+
"(Zdinx/D) instruction set extensions");
2259922600
}
2260022601

2260122602
const Function &Func = MF.getFunction();
2260222603
if (Func.hasFnAttribute("interrupt")) {
2260322604
if (!Func.arg_empty())
22604-
report_fatal_error(
22605-
"Functions with the interrupt attribute cannot have arguments!");
22605+
reportFatalUsageError(
22606+
"Functions with the interrupt attribute cannot have arguments!");
2260622607

2260722608
StringRef Kind =
2260822609
MF.getFunction().getFnAttribute("interrupt").getValueAsString();
@@ -22618,11 +22619,12 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
2261822619
"SiFive-CLIC-preemptible-stack-swap",
2261922620
};
2262022621
if (!llvm::is_contained(SupportedInterruptKinds, Kind))
22621-
report_fatal_error(
22622-
"Function interrupt attribute argument not supported!");
22622+
reportFatalUsageError(
22623+
"Function interrupt attribute argument not supported!");
2262322624

2262422625
if (Kind.starts_with("qci-") && !Subtarget.hasVendorXqciint())
22625-
report_fatal_error("'qci-*' interrupt kinds require Xqciint extension");
22626+
reportFatalUsageError(
22627+
"'qci-*' interrupt kinds require Xqciint extension");
2262622628

2262722629
if (Kind.starts_with("SiFive-CLIC-") && !Subtarget.hasVendorXSfmclic())
2262822630
reportFatalUsageError(
@@ -22860,7 +22862,7 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
2286022862

2286122863
if (CallConv == CallingConv::GHC) {
2286222864
if (Subtarget.hasStdExtE())
22863-
report_fatal_error("GHC calling convention is not supported on RVE!");
22865+
reportFatalUsageError("GHC calling convention is not supported on RVE!");
2286422866
ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV_GHC);
2286522867
} else
2286622868
analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI,
@@ -22874,8 +22876,8 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
2287422876
if (IsTailCall)
2287522877
++NumTailCalls;
2287622878
else if (CLI.CB && CLI.CB->isMustTailCall())
22877-
report_fatal_error("failed to perform tail call elimination on a call "
22878-
"site marked musttail");
22879+
reportFatalInternalError("failed to perform tail call elimination on a "
22880+
"call site marked musttail");
2287922881

2288022882
// Get a count of how many bytes are to be pushed on the stack.
2288122883
unsigned NumBytes = ArgCCInfo.getStackSize();
@@ -23200,7 +23202,7 @@ RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2320023202
nullptr, CC_RISCV);
2320123203

2320223204
if (CallConv == CallingConv::GHC && !RVLocs.empty())
23203-
report_fatal_error("GHC functions return void only");
23205+
reportFatalUsageError("GHC functions return void only");
2320423206

2320523207
SDValue Glue;
2320623208
SmallVector<SDValue, 4> RetOps(1, Chain);
@@ -23266,7 +23268,7 @@ RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2326623268
const Function &Func = DAG.getMachineFunction().getFunction();
2326723269
if (Func.hasFnAttribute("interrupt")) {
2326823270
if (!Func.getReturnType()->isVoidTy())
23269-
report_fatal_error(
23271+
reportFatalUsageError(
2327023272
"Functions with the interrupt attribute must have void return type!");
2327123273

2327223274
MachineFunction &MF = DAG.getMachineFunction();
@@ -24533,8 +24535,8 @@ RISCVTargetLowering::getRegisterByName(const char *RegName, LLT VT,
2453324535

2453424536
BitVector ReservedRegs = Subtarget.getRegisterInfo()->getReservedRegs(MF);
2453524537
if (!ReservedRegs.test(Reg) && !Subtarget.isRegisterReservedByUser(Reg))
24536-
report_fatal_error(Twine("Trying to obtain non-reserved register \"" +
24537-
StringRef(RegName) + "\"."));
24538+
reportFatalUsageError(Twine("Trying to obtain non-reserved register \"" +
24539+
StringRef(RegName) + "\"."));
2453824540
return Reg;
2453924541
}
2454024542

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -170,7 +170,7 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
170170

171171
if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {
172172
if (Subtarget.hasStdExtE())
173-
report_fatal_error("Graal reserved registers do not exist in RVE");
173+
reportFatalUsageError("Graal reserved registers do not exist in RVE");
174174
markSuperRegs(Reserved, RISCV::X23_H);
175175
markSuperRegs(Reserved, RISCV::X27_H);
176176
}
@@ -216,7 +216,7 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
216216
const int64_t NumOfVReg = Offset.getScalable() / 8;
217217
const int64_t FixedOffset = NumOfVReg * VLENB;
218218
if (!isInt<32>(FixedOffset)) {
219-
report_fatal_error(
219+
reportFatalUsageError(
220220
"Frame size outside of the signed 32-bit range not supported");
221221
}
222222
Offset = StackOffset::getFixed(FixedOffset + Offset.getFixed());
@@ -511,7 +511,7 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
511511
Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
512512

513513
if (!isInt<32>(Offset.getFixed())) {
514-
report_fatal_error(
514+
reportFatalUsageError(
515515
"Frame offsets outside of the signed 32-bit range not supported");
516516
}
517517

‎llvm/test/CodeGen/RISCV/get-register-reserve.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: not --crash llc < %s -mtriple=riscv32 -mattr +reserve-x8 2>&1 \
2+
; RUN: not llc < %s -mtriple=riscv32 -mattr +reserve-x8 2>&1 \
33
; RUN: | FileCheck -check-prefix=NO-RESERVE-A1 %s
4-
; RUN: not --crash llc < %s -mtriple=riscv32 -mattr +reserve-x11 2>&1 \
4+
; RUN: not llc < %s -mtriple=riscv32 -mattr +reserve-x11 2>&1 \
55
; RUN: | FileCheck -check-prefix=NO-RESERVE-FP %s
66
; RUN: llc < %s -mtriple=riscv32 -mattr +reserve-x8 -mattr +reserve-x11 \
77
; RUN: | FileCheck -check-prefix=RESERVE %s

‎llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \
1+
; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
22
; RUN: 2>&1 | FileCheck %s
3-
; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \
3+
; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
44
; RUN: 2>&1 | FileCheck %s
55

66
; CHECK: LLVM ERROR: Functions with the interrupt attribute cannot have arguments!

‎llvm/test/CodeGen/RISCV/interrupt-attr-invalid.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \
1+
; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
22
; RUN: 2>&1 | FileCheck %s
3-
; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \
3+
; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
44
; RUN: 2>&1 | FileCheck %s
55

66
; CHECK: LLVM ERROR: Function interrupt attribute argument not supported!

‎llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \
1+
; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
22
; RUN: 2>&1 | FileCheck %s
3-
; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \
3+
; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
44
; RUN: 2>&1 | FileCheck %s
55

66
; CHECK: LLVM ERROR: Functions with the interrupt attribute must have void return type!

‎llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
44
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvknhb \
55
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
6-
; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \
6+
; RUN: sed 's/iXLen/i32/g' %s | not llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \
77
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
8-
; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \
8+
; RUN: sed 's/iXLen/i64/g' %s | not llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \
99
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
1010

1111
; CHECK-ERROR: LLVM ERROR: SEW=64 needs Zvknhb to be enabled.

‎llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
44
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvknhb \
55
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
6-
; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \
6+
; RUN: sed 's/iXLen/i32/g' %s | not llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \
77
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
8-
; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \
8+
; RUN: sed 's/iXLen/i64/g' %s | not llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \
99
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
1010

1111
; CHECK-ERROR: LLVM ERROR: SEW=64 needs Zvknhb to be enabled.

‎llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
44
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvknha,+zvknhb \
55
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
6-
; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \
6+
; RUN: sed 's/iXLen/i32/g' %s | not llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \
77
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
8-
; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \
8+
; RUN: sed 's/iXLen/i64/g' %s | not llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \
99
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
1010

1111
; CHECK-ERROR: LLVM ERROR: SEW=64 needs Zvknhb to be enabled.

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