diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 796d5064ec9a4..3b738e4cc11a1 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -234,7 +234,7 @@ def FeatureStdExtZtso def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">, AssemblerPredicate<(all_of FeatureStdExtZtso), "'Ztso' (Memory Model - Total Store Order)">; -def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">; +def NoStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">; def FeatureStdExtZa64rs : RISCVExtension<1, 0, "Reservation Set Size of at Most 64 Bytes">; @@ -473,7 +473,7 @@ def FeatureStdExtZba def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">, AssemblerPredicate<(all_of FeatureStdExtZba), "'Zba' (Address Generation Instructions)">; -def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">; +def NoStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">; def FeatureStdExtZbb : RISCVExtension<1, 0, "Basic Bit-Manipulation">, @@ -1408,7 +1408,7 @@ def HasVendorXMIPSCBOP : Predicate<"Subtarget->hasVendorXMIPSCBOP()">, AssemblerPredicate<(all_of FeatureVendorXMIPSCBOP), "'Xmipscbop' (MIPS hardware prefetch)">; -def NotHasVendorXMIPSCBOP : Predicate<"!Subtarget->hasVendorXMIPSCBOP()">; +def NoVendorXMIPSCBOP : Predicate<"!Subtarget->hasVendorXMIPSCBOP()">; // WCH / Nanjing Qinheng Microelectronics Extension(s) diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td index 20ade6c39a8cf..791efca09d40e 100644 --- a/llvm/lib/Target/RISCV/RISCVGISel.td +++ b/llvm/lib/Target/RISCV/RISCVGISel.td @@ -147,7 +147,7 @@ def : Pat<(i32 (trunc GPR:$src)), (COPY GPR:$src)>; def : Pat<(zext_is_sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>; } -let Predicates = [IsRV64, NotHasStdExtZba] in +let Predicates = [IsRV64, NoStdExtZba] in def : Pat<(zext (i32 GPR:$src)), (SRLI (i64 (SLLI GPR:$src, 32)), 32)>; let Predicates = [IsRV32, NoStdExtZbb, NoStdExtZbkb] in diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 836a2b166feb9..23f5a848137c4 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2139,14 +2139,14 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), /// RV64 patterns -let Predicates = [IsRV64, NotHasStdExtZba] in { +let Predicates = [IsRV64, NoStdExtZba] in { def : Pat<(i64 (and GPR:$rs1, 0xffffffff)), (SRLI (i64 (SLLI GPR:$rs1, 32)), 32)>; // If we're shifting a 32-bit zero extended value left by 0-31 bits, use 2 // shifts instead of 3. This can occur when unsigned is used to index an array. def : Pat<(i64 (shl (and GPR:$rs1, 0xffffffff), uimm5:$shamt)), (SRLI (i64 (SLLI GPR:$rs1, 32)), (ImmSubFrom32 uimm5:$shamt))>; -} +} // Predicates = [IsRV64, NoStdExtZba] class binop_allhusers : PatFrag<(ops node:$lhs, node:$rhs), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td index e307f1a595880..48aac985230be 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td @@ -190,7 +190,7 @@ let Predicates = [HasAtomicLdSt, IsRV64] in { multiclass AMOPat ExtraPreds = []> { -let Predicates = !listconcat([HasStdExtA, NotHasStdExtZtso], ExtraPreds) in { +let Predicates = !listconcat([HasStdExtA, NoStdExtZtso], ExtraPreds) in { def : PatGprGpr(AtomicOp#"_monotonic"), !cast(BaseInst), vt>; def : PatGprGpr(AtomicOp#"_acquire"), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td index c1f67f77d7b84..fdf0195a2b669 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td @@ -111,11 +111,11 @@ def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))), (REMW GPR:$rs1, GPR:$rs2)>; } // Predicates = [HasStdExtM, IsRV64] -let Predicates = [HasStdExtZmmul, IsRV64, NotHasStdExtZba] in { +let Predicates = [HasStdExtZmmul, IsRV64, NoStdExtZba] in { // Special case for calculating the full 64-bit product of a 32x32 unsigned // multiply where the inputs aren't known to be zero extended. We can shift the // inputs left by 32 and use a MULHU. This saves two SRLIs needed to finish // zeroing the upper 32 bits. def : Pat<(i64 (mul (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff))), (MULHU (i64 (SLLI GPR:$rs1, 32)), (i64 (SLLI GPR:$rs2, 32)))>; -} // Predicates = [HasStdExtZmmul, IsRV64, NotHasStdExtZba] +} // Predicates = [HasStdExtZmmul, IsRV64, NoStdExtZba] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td index 77692f7cd3bee..7cf6d5ff762ff 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td @@ -70,7 +70,7 @@ defm AMOCAS_Q : AMO_cas_aq_rl<0b00101, 0b100, "amocas.q", GPRPairRV64>; multiclass AMOCASPat ExtraPreds = []> { - let Predicates = !listconcat([HasStdExtZacas, NotHasStdExtZtso], ExtraPreds) in { + let Predicates = !listconcat([HasStdExtZacas, NoStdExtZtso], ExtraPreds) in { def : Pat<(!cast(AtomicOp#"_monotonic") (vt GPR:$addr), (vt GPR:$cmp), (vt GPR:$new)), @@ -91,7 +91,7 @@ multiclass AMOCASPat(BaseInst#"_AQ_RL") GPR:$cmp, GPR:$addr, GPR:$new)>; - } // Predicates = !listconcat([HasStdExtZacas, NotHasStdExtZtso], ExtraPreds) + } // Predicates = !listconcat([HasStdExtZacas, NoStdExtZtso], ExtraPreds) let Predicates = !listconcat([HasStdExtZacas, HasStdExtZtso], ExtraPreds) in { def : Pat<(!cast(AtomicOp#"_monotonic") (vt GPR:$addr), (vt GPR:$cmp), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td index 0723b2f568a79..3ddcb1d615dbb 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td @@ -58,11 +58,11 @@ let Predicates = [HasStdExtZicboz] in { def CBO_ZERO : CBO_r<0b000000000100, "cbo.zero">, Sched<[]>; } // Predicates = [HasStdExtZicboz] -let Predicates = [HasStdExtZicbop, NotHasVendorXMIPSCBOP] in { +let Predicates = [HasStdExtZicbop, NoVendorXMIPSCBOP] in { def PREFETCH_I : Prefetch_ri<0b00000, "prefetch.i">, Sched<[]>; def PREFETCH_R : Prefetch_ri<0b00001, "prefetch.r">, Sched<[]>; def PREFETCH_W : Prefetch_ri<0b00011, "prefetch.w">, Sched<[]>; -} // Predicates = [HasStdExtZicbop] +} // Predicates = [HasStdExtZicbop, NoVendorXMIPSCBOP] //===----------------------------------------------------------------------===// // Patterns @@ -70,7 +70,7 @@ def PREFETCH_W : Prefetch_ri<0b00011, "prefetch.w">, Sched<[]>; def AddrRegImmLsb00000 : ComplexPattern; -let Predicates = [HasStdExtZicbop, NotHasVendorXMIPSCBOP] in { +let Predicates = [HasStdExtZicbop, NoVendorXMIPSCBOP] in { def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12), timm, timm, (i32 0)), (PREFETCH_I GPR:$rs1, simm12_lsb00000:$imm12)>; @@ -80,4 +80,4 @@ let Predicates = [HasStdExtZicbop, NotHasVendorXMIPSCBOP] in { def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12), (i32 1), timm, (i32 1)), (PREFETCH_W GPR:$rs1, simm12_lsb00000:$imm12)>; -} +} // Predicates = [HasStdExtZicbop, NoVendorXMIPSCBOP]