diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 6c6ae782f779f..0ef65a32e8163 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -383,6 +383,8 @@ class AArch64TargetLowering : public TargetLowering {
     return true;
   }
 
+  bool isCtlzFast() const override { return true; }
+
   bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
 
   bool hasAndNotCompare(SDValue V) const override {
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 12d2d678ff63a..945eba24b5a32 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -21387,6 +21387,10 @@ bool ARMTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
   return Subtarget->hasV6T2Ops();
 }
 
+bool ARMTargetLowering::isCtlzFast() const {
+  return Subtarget->hasV5TOps() && !Subtarget->isThumb1Only();
+}
+
 bool ARMTargetLowering::isMaskAndCmp0FoldingBeneficial(
     const Instruction &AndI) const {
   if (!Subtarget->hasV7Ops())
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 0185c8ddd4928..a254d0965d81d 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -651,6 +651,8 @@ class VectorType;
       return Opc != ISD::VECREDUCE_ADD;
     }
 
+    bool isCtlzFast() const override;
+
     /// Returns true if an argument of type Ty needs to be passed in a
     /// contiguous block of registers in calling convention CallConv.
     bool functionArgumentNeedsConsecutiveRegisters(