chore: rename modules and files

maksyuki · maksyuki · commit 7ebffe6415b3 · 2023-02-26T21:23:16.000+08:00
diff --git a/gowin/spinal/hw/spinal/axi4ddr3/Config.scala b/gowin/spinal/hw/spinal/axi4ddr3/Config.scala
@@ -10,5 +10,5 @@ object Config {
 }
 
 object GOWIN_AXI4_DDR3 extends App {
-  Config.spinal.generateVerilog(Paski_GowinDDR_AXI4(ClockDomain.external("sys_clk"), ClockDomain.external("mem_clk")))
+  Config.spinal.generateVerilog(GowinDDR_AXI4(ClockDomain.external("sys_clk"), ClockDomain.external("mem_clk")))
 }
diff --git a/gowin/spinal/hw/spinal/axi4ddr3/GowinDDR_AXI4.scala b/gowin/spinal/hw/spinal/axi4ddr3/GowinDDR_AXI4.scala
@@ -5,22 +5,22 @@ import spinal.lib.bus.amba4.axi.Axi4Shared
 import spinal.lib.{master, slave}
 
 // sys_clk: 27MHz mem_clk: 400MHz
-case class Paski_GowinDDR_AXI4(sys_clk: ClockDomain, mem_clk: ClockDomain) extends Component {
+case class GowinDDR_AXI4(sys_clk: ClockDomain, mem_clk: ClockDomain) extends Component {
 
   val gowin_DDR3 = Gowin_DDR3(
     sys_clk,
     mem_clk
   )
   val ddr_ref_clk = gowin_DDR3.clk_out
 
-  val axi4cache = Paski_GowinDDR_AXI4WithCache(
+  val axi4cache = GowinDDR_AXI4WithCache(
     sys_clk,
     32,
     27,
     4
   )
 
-  val axi4ctrl = Paski_GowinDDR14_Controller(
+  val axi4ctrl = GowinDDR14_Controller(
     sys_clk,
     ddr_ref_clk,
     contextType = axi4cache.context_type,
diff --git a/gowin/spinal/hw/spinal/axi4ddr3/GowinDDR_AXI4WithCache.scala b/gowin/spinal/hw/spinal/axi4ddr3/GowinDDR_AXI4WithCache.scala
@@ -9,7 +9,7 @@ import spinal.lib.{master, slave, Stream}
 // val last = Bool()
 // }
 
-case class Paski_GowinDDR_AXI4WithCache(sys_clk: ClockDomain, dataWidth: Int, axiaddrlen: Int, idWidth: Int, addrlen: Int = 27, burstlen: Int = 6) extends Component {
+case class GowinDDR_AXI4WithCache(sys_clk: ClockDomain, dataWidth: Int, axiaddrlen: Int, idWidth: Int, addrlen: Int = 27, burstlen: Int = 6) extends Component {
 
   val sys_clk_inst = sys_clk
 
diff --git a/gowin/spinal/hw/spinal/axi4ddr3/GowinDDR_Controller.scala b/gowin/spinal/hw/spinal/axi4ddr3/GowinDDR_Controller.scala
@@ -21,7 +21,7 @@ case class Paski_GowinDDR_PayloadRSP[T <: Data](contextType: T) extends Bundle {
   val context  = cloneOf(contextType)
 }
 
-case class Paski_GowinDDR14_Controller[T <: Data](sys_clk: ClockDomain, ddr_ref_clk: ClockDomain, addrlen: Int = 27, burstlen: Int = 6, fifo_length: Int = 32, contextType: T) extends Component {
+case class GowinDDR14_Controller[T <: Data](sys_clk: ClockDomain, ddr_ref_clk: ClockDomain, addrlen: Int = 27, burstlen: Int = 6, fifo_length: Int = 32, contextType: T) extends Component {
 
   val sys_clk_inst     = sys_clk
   val ddr_ref_clk_inst = ddr_ref_clk

Original file line number	Diff line number	Diff line change
`@@ -10,5 +10,5 @@ object Config {`
`10`	`10`	`}`
`11`	`11`
`12`	`12`	`object GOWIN_AXI4_DDR3 extends App {`
`13`		`- Config.spinal.generateVerilog(Paski_GowinDDR_AXI4(ClockDomain.external("sys_clk"), ClockDomain.external("mem_clk")))`
	`13`	`+ Config.spinal.generateVerilog(GowinDDR_AXI4(ClockDomain.external("sys_clk"), ClockDomain.external("mem_clk")))`
`14`	`14`	`}`
Original file line number	Diff line number	Diff line change
`@@ -21,7 +21,7 @@ case class Paski_GowinDDR_PayloadRSP[T <: Data](contextType: T) extends Bundle {`
`21`	`21`	`val context = cloneOf(contextType)`
`22`	`22`	`}`
`23`	`23`
`24`		`-case class Paski_GowinDDR14_Controller[T <: Data](sys_clk: ClockDomain, ddr_ref_clk: ClockDomain, addrlen: Int = 27, burstlen: Int = 6, fifo_length: Int = 32, contextType: T) extends Component {`
	`24`	`+case class GowinDDR14_Controller[T <: Data](sys_clk: ClockDomain, ddr_ref_clk: ClockDomain, addrlen: Int = 27, burstlen: Int = 6, fifo_length: Int = 32, contextType: T) extends Component {`
`25`	`25`
`26`	`26`	`val sys_clk_inst = sys_clk`
`27`	`27`	`val ddr_ref_clk_inst = ddr_ref_clk`