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maksyukimaksyuki
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feat: add contious ddr wt and rd test
1 parent 6eacc88 commit eab5cc5

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2 files changed

+70
-66
lines changed

2 files changed

+70
-66
lines changed

‎gowin/tester/bare_tester.v

Lines changed: 70 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -14,129 +14,136 @@ module bare_tester (
1414
input app_wdata_rdy,
1515
input app_rdata_valid,
1616
input app_rdata_end,
17-
input [127:0] app_rdata,
18-
19-
// test
20-
output [31:0] test_pin
17+
input [127:0] app_rdata
2118
);
2219

2320

24-
localparam WORK_WAIT_INIT = 3'd0;
25-
localparam WORK_FILL_INIT = 3'd1;
26-
localparam WORK_FILL_WT = 3'd2;
27-
localparam WORK_CHECK_INIT = 3'd3;
28-
localparam WORK_CHECK_RD = 3'd4;
29-
localparam WORK_CHECK_COMP = 3'd5;
21+
localparam FSM_WAIT_INIT = 3'd0;
22+
localparam FSM_FILL_INIT = 3'd1;
23+
localparam FSM_FILL_WT = 3'd2;
24+
localparam FSM_CHECK_INIT = 3'd3;
25+
localparam FSM_CHECK_RD = 3'd4;
26+
localparam FSM_CHECK_COMP = 3'd5;
27+
localparam FSM_CHECK_FAIL = 3'd6;
3028

3129
localparam WR_CMD = 3'h0;
3230
localparam RD_CMD = 3'h1;
31+
localparam INIT_DATA = 128'h0123_4567_890A_BCDE_FEDC_BA98_7654_3218;
32+
localparam DATA_NUM = 4;
3333

34-
reg [ 3:0] work_state;
34+
reg [ 3:0] state;
3535
reg [ 26:0] int_app_addr;
3636

37-
reg [ 7:0] work_counter;
38-
reg [ 5:0] wr_cnt;
37+
reg [ 7:0] init_cnt;
38+
reg [ 5:0] wt_cnt;
3939

4040
reg [127:0] rdata_buf [5:0];
4141
reg [ 2:0] rdata_idx;
42+
reg sw_flag;
43+
reg [ 2:0] addr_offset;
4244

45+
initial begin
46+
for (integer i = 0; i < 6; i = i + 1) begin
47+
rdata_buf[i] <= 'd0;
48+
end
49+
end
4350
// int_app_addr: bank: [3bit] row: [13bit] col: [10bit]
4451
assign app_addr = {1'b0, int_app_addr};
4552

4653
always @(posedge clk or negedge rstn) begin
4754
if (rstn == 1'b0) begin
48-
work_state <= WORK_WAIT_INIT;
49-
50-
int_app_addr <= 27'd0;
51-
app_burst_number <= 6'd0;
52-
app_cmd_en <= 1'b0;
53-
app_cmd <= 3'd0;
54-
app_wdata_en <= 1'b0;
55-
app_wdata_end <= 1'b0;
56-
app_wdata <= 128'd0;
57-
58-
work_counter <= 8'd0;
59-
wr_cnt <= 6'd0;
60-
rdata_idx <= 3'd0;
55+
state <= FSM_WAIT_INIT;
56+
57+
int_app_addr <= 'd0;
58+
app_burst_number <= 'd0;
59+
app_cmd_en <= 'b0;
60+
app_cmd <= 'd0;
61+
app_wdata_en <= 'b0;
62+
app_wdata_end <= 'b0;
63+
app_wdata <= 'd0;
64+
init_cnt <= 'd0;
65+
wt_cnt <= 'd0;
66+
rdata_idx <= 'd0;
67+
addr_offset <= 'd0;
68+
sw_flag <= 'd0;
6169
end else begin
62-
// read_buf_s1 <= read_buf_s0;
63-
// read_buf_s0 <= read_data[read_data_pos];
64-
work_counter <= work_counter + 1'd1;
65-
case (work_state)
66-
WORK_WAIT_INIT: begin
67-
if (init_calib_complete == 1'b0) work_counter <= 8'd0;
68-
if (work_counter == 8'd255) work_state <= WORK_FILL_INIT;
70+
init_cnt <= init_cnt + 1'd1;
71+
case (state)
72+
FSM_WAIT_INIT: begin
73+
if (init_calib_complete == 1'b0) init_cnt <= 8'd0;
74+
if (init_cnt == 8'd255) state <= FSM_FILL_INIT;
6975
end
7076

71-
WORK_FILL_INIT: begin
77+
FSM_FILL_INIT: begin
7278
if (app_cmd_rdy && app_wdata_rdy) begin
7379
app_cmd_en <= 1'd1;
7480
app_cmd <= WR_CMD;
75-
int_app_addr <= 27'd0;
76-
app_burst_number <= 6'd3;
77-
work_state <= WORK_FILL_WT;
78-
81+
int_app_addr <= addr_offset;
82+
app_wdata <= (~addr_offset) ? INIT_DATA : app_wdata + 1;
83+
app_burst_number <= DATA_NUM - 1;
84+
state <= FSM_FILL_WT;
7985
app_wdata_en <= 1'd1;
8086
app_wdata_end <= 1'd1;
81-
app_wdata <= 128'h0123_4567_890A_BCDE_FEDC_BA98_7654_3210;
82-
wr_cnt <= wr_cnt + 1'd1;
87+
wt_cnt <= 'd0;
8388
end
8489
end
8590

86-
WORK_FILL_WT: begin
91+
FSM_FILL_WT: begin
8792
app_cmd_en <= 1'd0;
8893
if (app_wdata_rdy) begin
89-
if (wr_cnt == 6'd3) begin
90-
app_wdata_en <= 1'd0;
91-
app_wdata_end <= 1'd0;
92-
wr_cnt <= 6'd0;
93-
work_state <= WORK_CHECK_INIT;
94+
if (wt_cnt == DATA_NUM - 1) begin
95+
app_wdata_en <= 'd0;
96+
app_wdata_end <= 'd0;
97+
app_wdata <= 'd0;
98+
wt_cnt <= 'd0;
99+
state <= FSM_CHECK_INIT;
94100
end else begin
95101
app_wdata_en <= 1'd1;
96102
app_wdata_end <= 1'd1;
97-
app_wdata <= 128'h0123_4567_890A_BCDE_FEDC_BA98_7654_3210;
98-
wr_cnt <= wr_cnt + 1'd1;
103+
app_wdata <= app_wdata + 1'd1;
104+
wt_cnt <= wt_cnt + 1'd1;
99105
end
100106
end else begin
101107
app_wdata_en <= 1'd0;
102108
app_wdata_end <= 1'd0;
103109
end
104110
end
105111

106-
WORK_CHECK_INIT: begin
112+
FSM_CHECK_INIT: begin
107113
if (app_cmd_rdy) begin
108114
app_cmd_en <= 1'd1;
109115
app_cmd <= RD_CMD;
110-
int_app_addr <= 27'd0;
111-
app_burst_number <= 6'd3;
112-
work_state <= WORK_CHECK_RD;
113-
rdata_idx <= 3'd0;
116+
int_app_addr <= addr_offset; // because wt add
117+
app_burst_number <= DATA_NUM - 1;
118+
state <= FSM_CHECK_RD;
119+
rdata_idx <= 'd0;
114120
end
115121
end
116122

117-
WORK_CHECK_RD: begin
123+
FSM_CHECK_RD: begin
118124
app_cmd_en <= 1'd0;
119125
if (app_rdata_valid) begin
120-
rdata_buf[rdata_idx] <= app_rdata;
121-
rdata_idx <= rdata_idx + 1'd1;
122126
if (rdata_idx == 3'd3) begin
123-
work_state <= WORK_CHECK_COMP;
124-
rdata_idx <= 3'd0;
127+
state <= FSM_FILL_INIT;
128+
rdata_idx <= 'd0;
129+
addr_offset <= addr_offset + 1;
125130
end
131+
rdata_buf[rdata_idx] <= app_rdata;
132+
rdata_idx <= rdata_idx + 1'd1;
126133
end
127134
end
128135

129-
WORK_CHECK_COMP: begin
136+
FSM_CHECK_COMP: begin
137+
138+
end
139+
FSM_CHECK_FAIL: begin
130140

131141
end
132142
default: begin
133-
work_state <= WORK_WAIT_INIT;
143+
state <= FSM_WAIT_INIT;
134144
end
135145
endcase
136146

137147
end
138148
end
139-
140-
assign test_pin = rdata_buf[0];
141-
142149
endmodule

‎gowin/top/bare_ddr3_top.v

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -34,16 +34,13 @@ module bare_ddr3_top (
3434
wire init_calib_complete;
3535
wire [ 5:0] app_burst_number;
3636
wire [ 27:0] app_addr;
37-
// ddr3 cmd channel
3837
wire app_cmd_en;
3938
wire [ 2:0] app_cmd;
4039
wire app_cmd_rdy;
41-
// ddr3 w channel
4240
wire app_wdata_en;
4341
wire app_wdata_end;
4442
wire [127:0] app_wdata;
4543
wire app_wdata_rdy;
46-
// ddr3 r channel
4744
wire app_rdata_valid;
4845
wire app_rdata_end;
4946
wire [127:0] app_rdata;

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