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[AArch64][SVE2] Asm: add various bitwise shift instructions
Summary: This patch adds support for the SVE2 saturating/rounding bitwise shift left (predicated) group of instructions: * SRSHL, URSHL, SRSHLR, URSHLR, SQSHL, UQSHL, SQRSHL, UQRSHL, SQSHLR, UQSHLR, SQRSHLR, UQRSHLR Immediate forms of the SQSHL and UQSHL instructions are also added to the existing SVE bitwise shift by immediate (predicated) group, as well as three new instructions SRSHR/URSHR/SQSHLU. The new instructions in this group are encoded similarly and are implemented using the same TableGen class with a minimal change (1 bit in encoding). The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62140 llvm-svn: 361612
1 parent 6bca64f commit 968cb0e

32 files changed

+1935
-11
lines changed

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 25 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -875,10 +875,10 @@ let Predicates = [HasSVE] in {
875875
defm LSL_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b11, "lsl">;
876876

877877
// Predicated shifts
878-
defm ASR_ZPmI : sve_int_bin_pred_shift_imm_right<0b000, "asr">;
879-
defm LSR_ZPmI : sve_int_bin_pred_shift_imm_right<0b001, "lsr">;
880-
defm LSL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b011, "lsl">;
881-
defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<0b100, "asrd">;
878+
defm ASR_ZPmI : sve_int_bin_pred_shift_imm_right<0b0000, "asr">;
879+
defm LSR_ZPmI : sve_int_bin_pred_shift_imm_right<0b0001, "lsr">;
880+
defm LSL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0011, "lsl">;
881+
defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<0b0100, "asrd">;
882882

883883
defm ASR_ZPmZ : sve_int_bin_pred_shift<0b000, "asr">;
884884
defm LSR_ZPmZ : sve_int_bin_pred_shift<0b001, "lsr">;
@@ -1150,11 +1150,32 @@ let Predicates = [HasSVE2] in {
11501150
defm SQSUBR_ZPmZ : sve2_int_arith_pred<0b111100, "sqsubr">;
11511151
defm UQSUBR_ZPmZ : sve2_int_arith_pred<0b111110, "uqsubr">;
11521152

1153+
// SVE2 saturating/rounding bitwise shift left (predicated)
1154+
defm SRSHL_ZPmZ : sve2_int_arith_pred<0b000100, "srshl">;
1155+
defm URSHL_ZPmZ : sve2_int_arith_pred<0b000110, "urshl">;
1156+
defm SRSHLR_ZPmZ : sve2_int_arith_pred<0b001100, "srshlr">;
1157+
defm URSHLR_ZPmZ : sve2_int_arith_pred<0b001110, "urshlr">;
1158+
defm SQSHL_ZPmZ : sve2_int_arith_pred<0b010000, "sqshl">;
1159+
defm UQSHL_ZPmZ : sve2_int_arith_pred<0b010010, "uqshl">;
1160+
defm SQRSHL_ZPmZ : sve2_int_arith_pred<0b010100, "sqrshl">;
1161+
defm UQRSHL_ZPmZ : sve2_int_arith_pred<0b010110, "uqrshl">;
1162+
defm SQSHLR_ZPmZ : sve2_int_arith_pred<0b011000, "sqshlr">;
1163+
defm UQSHLR_ZPmZ : sve2_int_arith_pred<0b011010, "uqshlr">;
1164+
defm SQRSHLR_ZPmZ : sve2_int_arith_pred<0b011100, "sqrshlr">;
1165+
defm UQRSHLR_ZPmZ : sve2_int_arith_pred<0b011110, "uqrshlr">;
1166+
11531167
// SVE2 integer multiply long
11541168
defm SQDMULLB_ZZZ : sve2_wide_int_arith_long<0b11000, "sqdmullb">;
11551169
defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">;
11561170
defm SMULLB_ZZZ : sve2_wide_int_arith_long<0b11100, "smullb">;
11571171
defm SMULLT_ZZZ : sve2_wide_int_arith_long<0b11101, "smullt">;
11581172
defm UMULLB_ZZZ : sve2_wide_int_arith_long<0b11110, "umullb">;
11591173
defm UMULLT_ZZZ : sve2_wide_int_arith_long<0b11111, "umullt">;
1174+
1175+
// Predicated shifts
1176+
defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
1177+
defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;
1178+
defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">;
1179+
defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">;
1180+
defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">;
11601181
}

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2926,9 +2926,9 @@ multiclass sve_int_index_rr<string asm> {
29262926
//===----------------------------------------------------------------------===//
29272927
// SVE Bitwise Shift - Predicated Group
29282928
//===----------------------------------------------------------------------===//
2929-
class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<3> opc, string asm,
2930-
ZPRRegOp zprty, Operand immtype,
2931-
ElementSizeEnum size>
2929+
class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<4> opc, string asm,
2930+
ZPRRegOp zprty, Operand immtype,
2931+
ElementSizeEnum size>
29322932
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm),
29332933
asm, "\t$Zdn, $Pg/m, $_Zdn, $imm",
29342934
"",
@@ -2938,8 +2938,8 @@ class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<3> opc, string asm,
29382938
bits<6> imm;
29392939
let Inst{31-24} = 0b00000100;
29402940
let Inst{23-22} = tsz8_64{3-2};
2941-
let Inst{21-19} = 0b000;
2942-
let Inst{18-16} = opc;
2941+
let Inst{21-20} = 0b00;
2942+
let Inst{19-16} = opc;
29432943
let Inst{15-13} = 0b100;
29442944
let Inst{12-10} = Pg;
29452945
let Inst{9-8} = tsz8_64{1-0};
@@ -2951,7 +2951,7 @@ class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<3> opc, string asm,
29512951
let ElementSize = size;
29522952
}
29532953

2954-
multiclass sve_int_bin_pred_shift_imm_left<bits<3> opc, string asm> {
2954+
multiclass sve_int_bin_pred_shift_imm_left<bits<4> opc, string asm> {
29552955
def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8,
29562956
ElementSizeB>;
29572957
def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16,
@@ -2969,7 +2969,7 @@ multiclass sve_int_bin_pred_shift_imm_left<bits<3> opc, string asm> {
29692969
}
29702970
}
29712971

2972-
multiclass sve_int_bin_pred_shift_imm_right<bits<3> opc, string asm> {
2972+
multiclass sve_int_bin_pred_shift_imm_right<bits<4> opc, string asm> {
29732973
def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8,
29742974
ElementSizeB>;
29752975
def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16,

‎llvm/test/MC/AArch64/SVE2/sqrshl-diagnostics.s

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
2+
3+
// --------------------------------------------------------------------------//
4+
// Source and Destination Registers must match
5+
6+
sqrshl z0.b, p0/m, z1.b, z2.b
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
8+
// CHECK-NEXT: sqrshl z0.b, p0/m, z1.b, z2.b
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
12+
// --------------------------------------------------------------------------//
13+
// Element sizes must match
14+
15+
sqrshl z0.b, p0/m, z0.d, z1.d
16+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
17+
// CHECK-NEXT: sqrshl z0.b, p0/m, z0.d, z1.d
18+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
19+
20+
sqrshl z0.b, p0/m, z0.b, z1.h
21+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
22+
// CHECK-NEXT: sqrshl z0.b, p0/m, z0.b, z1.h
23+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
24+
25+
26+
// --------------------------------------------------------------------------//
27+
// Invalid predicate
28+
29+
sqrshl z0.b, p0/z, z0.b, z1.b
30+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
31+
// CHECK-NEXT: sqrshl z0.b, p0/z, z0.b, z1.b
32+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
33+
34+
sqrshl z0.b, p8/m, z0.b, z1.b
35+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
36+
// CHECK-NEXT: sqrshl z0.b, p8/m, z0.b, z1.b
37+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2/sqrshl.s

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
6+
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
8+
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9+
10+
sqrshl z0.b, p0/m, z0.b, z1.b
11+
// CHECK-INST: sqrshl z0.b, p0/m, z0.b, z1.b
12+
// CHECK-ENCODING: [0x20,0x80,0x0a,0x44]
13+
// CHECK-ERROR: instruction requires: sve2
14+
// CHECK-UNKNOWN: 20 80 0a 44 <unknown>
15+
16+
sqrshl z0.h, p0/m, z0.h, z1.h
17+
// CHECK-INST: sqrshl z0.h, p0/m, z0.h, z1.h
18+
// CHECK-ENCODING: [0x20,0x80,0x4a,0x44]
19+
// CHECK-ERROR: instruction requires: sve2
20+
// CHECK-UNKNOWN: 20 80 4a 44 <unknown>
21+
22+
sqrshl z29.s, p7/m, z29.s, z30.s
23+
// CHECK-INST: sqrshl z29.s, p7/m, z29.s, z30.s
24+
// CHECK-ENCODING: [0xdd,0x9f,0x8a,0x44]
25+
// CHECK-ERROR: instruction requires: sve2
26+
// CHECK-UNKNOWN: dd 9f 8a 44 <unknown>
27+
28+
sqrshl z31.d, p7/m, z31.d, z30.d
29+
// CHECK-INST: sqrshl z31.d, p7/m, z31.d, z30.d
30+
// CHECK-ENCODING: [0xdf,0x9f,0xca,0x44]
31+
// CHECK-ERROR: instruction requires: sve2
32+
// CHECK-UNKNOWN: df 9f ca 44 <unknown>
33+
34+
// --------------------------------------------------------------------------//
35+
// Test compatibility with MOVPRFX instruction.
36+
37+
movprfx z31.d, p0/z, z6.d
38+
// CHECK-INST: movprfx z31.d, p0/z, z6.d
39+
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
40+
// CHECK-ERROR: instruction requires: sve
41+
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
42+
43+
sqrshl z31.d, p0/m, z31.d, z30.d
44+
// CHECK-INST: sqrshl z31.d, p0/m, z31.d, z30.d
45+
// CHECK-ENCODING: [0xdf,0x83,0xca,0x44]
46+
// CHECK-ERROR: instruction requires: sve2
47+
// CHECK-UNKNOWN: df 83 ca 44 <unknown>
48+
49+
movprfx z31, z6
50+
// CHECK-INST: movprfx z31, z6
51+
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
52+
// CHECK-ERROR: instruction requires: sve
53+
// CHECK-UNKNOWN: df bc 20 04 <unknown>
54+
55+
sqrshl z31.d, p7/m, z31.d, z30.d
56+
// CHECK-INST: sqrshl z31.d, p7/m, z31.d, z30.d
57+
// CHECK-ENCODING: [0xdf,0x9f,0xca,0x44]
58+
// CHECK-ERROR: instruction requires: sve2
59+
// CHECK-UNKNOWN: df 9f ca 44 <unknown>

‎llvm/test/MC/AArch64/SVE2/sqrshlr-diagnostics.s

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
2+
3+
// --------------------------------------------------------------------------//
4+
// Source and Destination Registers must match
5+
6+
sqrshlr z0.b, p0/m, z1.b, z2.b
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
8+
// CHECK-NEXT: sqrshlr z0.b, p0/m, z1.b, z2.b
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
12+
// --------------------------------------------------------------------------//
13+
// Element sizes must match
14+
15+
sqrshlr z0.b, p0/m, z0.d, z1.d
16+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
17+
// CHECK-NEXT: sqrshlr z0.b, p0/m, z0.d, z1.d
18+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
19+
20+
sqrshlr z0.b, p0/m, z0.b, z1.h
21+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
22+
// CHECK-NEXT: sqrshlr z0.b, p0/m, z0.b, z1.h
23+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
24+
25+
26+
// --------------------------------------------------------------------------//
27+
// Invalid predicate
28+
29+
sqrshlr z0.b, p0/z, z0.b, z1.b
30+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
31+
// CHECK-NEXT: sqrshlr z0.b, p0/z, z0.b, z1.b
32+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
33+
34+
sqrshlr z0.b, p8/m, z0.b, z1.b
35+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
36+
// CHECK-NEXT: sqrshlr z0.b, p8/m, z0.b, z1.b
37+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2/sqrshlr.s

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
6+
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
8+
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9+
10+
sqrshlr z0.b, p0/m, z0.b, z1.b
11+
// CHECK-INST: sqrshlr z0.b, p0/m, z0.b, z1.b
12+
// CHECK-ENCODING: [0x20,0x80,0x0e,0x44]
13+
// CHECK-ERROR: instruction requires: sve2
14+
// CHECK-UNKNOWN: 20 80 0e 44 <unknown>
15+
16+
sqrshlr z0.h, p0/m, z0.h, z1.h
17+
// CHECK-INST: sqrshlr z0.h, p0/m, z0.h, z1.h
18+
// CHECK-ENCODING: [0x20,0x80,0x4e,0x44]
19+
// CHECK-ERROR: instruction requires: sve2
20+
// CHECK-UNKNOWN: 20 80 4e 44 <unknown>
21+
22+
sqrshlr z29.s, p7/m, z29.s, z30.s
23+
// CHECK-INST: sqrshlr z29.s, p7/m, z29.s, z30.s
24+
// CHECK-ENCODING: [0xdd,0x9f,0x8e,0x44]
25+
// CHECK-ERROR: instruction requires: sve2
26+
// CHECK-UNKNOWN: dd 9f 8e 44 <unknown>
27+
28+
sqrshlr z31.d, p7/m, z31.d, z30.d
29+
// CHECK-INST: sqrshlr z31.d, p7/m, z31.d, z30.d
30+
// CHECK-ENCODING: [0xdf,0x9f,0xce,0x44]
31+
// CHECK-ERROR: instruction requires: sve2
32+
// CHECK-UNKNOWN: df 9f ce 44 <unknown>
33+
34+
// --------------------------------------------------------------------------//
35+
// Test compatibility with MOVPRFX instruction.
36+
37+
movprfx z31.d, p0/z, z6.d
38+
// CHECK-INST: movprfx z31.d, p0/z, z6.d
39+
// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
40+
// CHECK-ERROR: instruction requires: sve
41+
// CHECK-UNKNOWN: df 20 d0 04 <unknown>
42+
43+
sqrshlr z31.d, p0/m, z31.d, z30.d
44+
// CHECK-INST: sqrshlr z31.d, p0/m, z31.d, z30.d
45+
// CHECK-ENCODING: [0xdf,0x83,0xce,0x44]
46+
// CHECK-ERROR: instruction requires: sve2
47+
// CHECK-UNKNOWN: df 83 ce 44 <unknown>
48+
49+
movprfx z31, z6
50+
// CHECK-INST: movprfx z31, z6
51+
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
52+
// CHECK-ERROR: instruction requires: sve
53+
// CHECK-UNKNOWN: df bc 20 04 <unknown>
54+
55+
sqrshlr z31.d, p7/m, z31.d, z30.d
56+
// CHECK-INST: sqrshlr z31.d, p7/m, z31.d, z30.d
57+
// CHECK-ENCODING: [0xdf,0x9f,0xce,0x44]
58+
// CHECK-ERROR: instruction requires: sve2
59+
// CHECK-UNKNOWN: df 9f ce 44 <unknown>

‎llvm/test/MC/AArch64/SVE2/sqshl-diagnostics.s

Lines changed: 98 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,98 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
2+
3+
sqshl z0.b, p0/m, z0.b, #-1
4+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
5+
// CHECK-NEXT: sqshl z0.b, p0/m, z0.b, #-1
6+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
7+
8+
sqshl z0.b, p0/m, z0.b, #8
9+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
10+
// CHECK-NEXT: sqshl z0.b, p0/m, z0.b, #8
11+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
12+
13+
sqshl z0.h, p0/m, z0.h, #-1
14+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
15+
// CHECK-NEXT: sqshl z0.h, p0/m, z0.h, #-1
16+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
17+
18+
sqshl z0.h, p0/m, z0.h, #16
19+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
20+
// CHECK-NEXT: sqshl z0.h, p0/m, z0.h, #16
21+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
22+
23+
sqshl z0.s, p0/m, z0.s, #-1
24+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
25+
// CHECK-NEXT: sqshl z0.s, p0/m, z0.s, #-1
26+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
27+
28+
sqshl z0.s, p0/m, z0.s, #32
29+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
30+
// CHECK-NEXT: sqshl z0.s, p0/m, z0.s, #32
31+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32+
33+
sqshl z0.d, p0/m, z0.d, #-1
34+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
35+
// CHECK-NEXT: sqshl z0.d, p0/m, z0.d, #-1
36+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
37+
38+
sqshl z0.d, p0/m, z0.d, #64
39+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
40+
// CHECK-NEXT: sqshl z0.d, p0/m, z0.d, #64
41+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
42+
43+
44+
// --------------------------------------------------------------------------//
45+
// Source and Destination Registers must match
46+
47+
sqshl z0.b, p0/m, z1.b, z2.b
48+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
49+
// CHECK-NEXT: sqshl z0.b, p0/m, z1.b, z2.b
50+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
51+
52+
sqshl z0.b, p0/m, z1.b, #0
53+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
54+
// CHECK-NEXT: sqshl z0.b, p0/m, z1.b, #0
55+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
56+
57+
58+
// --------------------------------------------------------------------------//
59+
// Element sizes must match
60+
61+
sqshl z0.b, p0/m, z0.d, z1.d
62+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
63+
// CHECK-NEXT: sqshl z0.b, p0/m, z0.d, z1.d
64+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
65+
66+
sqshl z0.b, p0/m, z0.b, z1.h
67+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
68+
// CHECK-NEXT: sqshl z0.b, p0/m, z0.b, z1.h
69+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
70+
71+
sqshl z0.b, p0/m, z0.d, #0
72+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
73+
// CHECK-NEXT: sqshl z0.b, p0/m, z0.d, #0
74+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
75+
76+
sqshl z0.d, p0/m, z0.b, #0
77+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
78+
// CHECK-NEXT: sqshl z0.d, p0/m, z0.b, #0
79+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
80+
81+
82+
// --------------------------------------------------------------------------//
83+
// Invalid predicate
84+
85+
sqshl z0.b, p0/z, z0.b, z1.b
86+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
87+
// CHECK-NEXT: sqshl z0.b, p0/z, z0.b, z1.b
88+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
89+
90+
sqshl z0.b, p8/m, z0.b, z1.b
91+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
92+
// CHECK-NEXT: sqshl z0.b, p8/m, z0.b, z1.b
93+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
94+
95+
sqshl z0.b, p8/m, z0.b, #0
96+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
97+
// CHECK-NEXT: sqshl z0.b, p8/m, z0.b, #0
98+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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