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Complete the missing parts of MIPS-JIT functionality. Patch by Petar Jovanovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@143014 91177308-0d34-0410-b5e6-96231b3b80d8
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8 files changed

+203
-121
lines changed

8 files changed

+203
-121
lines changed

‎lib/Target/Mips/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ set(LLVM_TARGET_DEFINITIONS Mips.td)
22

33
llvm_tablegen(MipsGenRegisterInfo.inc -gen-register-info)
44
llvm_tablegen(MipsGenInstrInfo.inc -gen-instr-info)
5+
llvm_tablegen(MipsGenCodeEmitter.inc -gen-emitter)
56
llvm_tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
67
llvm_tablegen(MipsGenDAGISel.inc -gen-dag-isel)
78
llvm_tablegen(MipsGenCallingConv.inc -gen-callingconv)

‎lib/Target/Mips/Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ TARGET = Mips
1313

1414
# Make sure that tblgen is run, first thing.
1515
BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
16-
MipsGenAsmWriter.inc \
16+
MipsGenAsmWriter.inc MipsGenCodeEmitter.inc \
1717
MipsGenDAGISel.inc MipsGenCallingConv.inc \
1818
MipsGenSubtargetInfo.inc
1919

‎lib/Target/Mips/Mips64InstrInfo.td

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -39,51 +39,51 @@ def imm32_63 : ImmLeaf<i64,
3939
// Shifts
4040
class LogicR_shift_rotate_imm64<bits<6> func, bits<5> _rs, string instr_asm,
4141
SDNode OpNode, PatFrag PF>:
42-
FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, shamt_64:$c),
43-
!strconcat(instr_asm, "\t$dst, $b, $c"),
44-
[(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, (i64 PF:$c)))],
42+
FR<0x00, func, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt, shamt_64:$shamt),
43+
!strconcat(instr_asm, "\t$rd, $rt, $shamt"),
44+
[(set CPU64Regs:$rd, (OpNode CPU64Regs:$rt, (i64 PF:$shamt)))],
4545
IIAlu> {
4646
let rs = _rs;
4747
}
4848

4949
class LogicR_shift_rotate_reg64<bits<6> func, bits<5> _shamt, string instr_asm,
5050
SDNode OpNode>:
51-
FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$c, CPU64Regs:$b),
52-
!strconcat(instr_asm, "\t$dst, $b, $c"),
53-
[(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], IIAlu> {
51+
FR<0x00, func, (outs CPU64Regs:$rd), (ins CPU64Regs:$rs, CPU64Regs:$rt),
52+
!strconcat(instr_asm, "\t$rd, $rt, $rs"),
53+
[(set CPU64Regs:$rd, (OpNode CPU64Regs:$rt, CPU64Regs:$rs))], IIAlu> {
5454
let shamt = _shamt;
5555
}
5656

5757
// Mul, Div
58-
let Defs = [HI64, LO64] in {
58+
let rd = 0, shamt = 0, Defs = [HI64, LO64] in {
5959
let isCommutable = 1 in
6060
class Mul64<bits<6> func, string instr_asm, InstrItinClass itin>:
61-
FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
62-
!strconcat(instr_asm, "\t$a, $b"), [], itin>;
61+
FR<0x00, func, (outs), (ins CPU64Regs:$rs, CPU64Regs:$rt),
62+
!strconcat(instr_asm, "\t$rs, $rt"), [], itin>;
6363

6464
class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
65-
FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
66-
!strconcat(instr_asm, "\t$$zero, $a, $b"),
67-
[(op CPU64Regs:$a, CPU64Regs:$b)], itin>;
65+
FR<0x00, func, (outs), (ins CPU64Regs:$rs, CPU64Regs:$rt),
66+
!strconcat(instr_asm, "\t$$zero, $rs, $rt"),
67+
[(op CPU64Regs:$rs, CPU64Regs:$rt)], itin>;
6868
}
6969

7070
// Move from Hi/Lo
7171
let shamt = 0 in {
7272
let rs = 0, rt = 0 in
7373
class MoveFromLOHI64<bits<6> func, string instr_asm>:
74-
FR<0x00, func, (outs CPU64Regs:$dst), (ins),
75-
!strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
74+
FR<0x00, func, (outs CPU64Regs:$rd), (ins),
75+
!strconcat(instr_asm, "\t$rd"), [], IIHiLo>;
7676

7777
let rt = 0, rd = 0 in
7878
class MoveToLOHI64<bits<6> func, string instr_asm>:
79-
FR<0x00, func, (outs), (ins CPU64Regs:$src),
80-
!strconcat(instr_asm, "\t$src"), [], IIHiLo>;
79+
FR<0x00, func, (outs), (ins CPU64Regs:$rs),
80+
!strconcat(instr_asm, "\t$rs"), [], IIHiLo>;
8181
}
8282

8383
// Count Leading Ones/Zeros in Word
8484
class CountLeading64<bits<6> func, string instr_asm, list<dag> pattern>:
85-
FR<0x1c, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$src),
86-
!strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
85+
FR<0x1c, func, (outs CPU64Regs:$rd), (ins CPU64Regs:$rs),
86+
!strconcat(instr_asm, "\t$rd, $rs"), pattern, IIAlu>,
8787
Requires<[HasBitCount]> {
8888
let shamt = 0;
8989
let rt = rd;
@@ -180,9 +180,9 @@ let Uses = [LO64] in
180180

181181
/// Count Leading
182182
def DCLZ : CountLeading64<0x24, "dclz",
183-
[(set CPU64Regs:$dst, (ctlz CPU64Regs:$src))]>;
183+
[(set CPU64Regs:$rd, (ctlz CPU64Regs:$rs))]>;
184184
def DCLO : CountLeading64<0x25, "dclo",
185-
[(set CPU64Regs:$dst, (ctlz (not CPU64Regs:$src)))]>;
185+
[(set CPU64Regs:$rd, (ctlz (not CPU64Regs:$rs)))]>;
186186

187187
//===----------------------------------------------------------------------===//
188188
// Arbitrary patterns that map to one or more instructions

‎lib/Target/Mips/MipsCodeEmitter.cpp

Lines changed: 26 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,9 @@ class MipsCodeEmitter : public MachineFunctionPass {
105105
unsigned getRelocation(const MachineInstr &MI,
106106
const MachineOperand &MO) const;
107107

108+
unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
109+
unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const;
110+
unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;
108111
};
109112
}
110113

@@ -153,6 +156,28 @@ unsigned MipsCodeEmitter::getRelocation(const MachineInstr &MI,
153156
return Mips::reloc_mips_lo;
154157
}
155158

159+
unsigned MipsCodeEmitter::getMemEncoding(const MachineInstr &MI,
160+
unsigned OpNo) const {
161+
// Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
162+
assert(MI.getOperand(OpNo).isReg());
163+
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo)) << 16;
164+
return
165+
(getMachineOpValue(MI, MI.getOperand(OpNo+1)) & 0xFFFF) | RegBits;
166+
}
167+
168+
unsigned MipsCodeEmitter::getSizeExtEncoding(const MachineInstr &MI,
169+
unsigned OpNo) const {
170+
// size is encoded as size-1.
171+
return getMachineOpValue(MI, MI.getOperand(OpNo)) - 1;
172+
}
173+
174+
unsigned MipsCodeEmitter::getSizeInsEncoding(const MachineInstr &MI,
175+
unsigned OpNo) const {
176+
// size is encoded as pos+size-1.
177+
return getMachineOpValue(MI, MI.getOperand(OpNo-1)) +
178+
getMachineOpValue(MI, MI.getOperand(OpNo)) - 1;
179+
}
180+
156181
/// getMachineOpValue - Return binary encoding of operand. If the machine
157182
/// operand requires relocation, record the relocation and return zero.
158183
unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI,
@@ -238,8 +263,4 @@ FunctionPass *llvm::createMipsJITCodeEmitterPass(MipsTargetMachine &TM,
238263
return new MipsCodeEmitter(TM, JCE);
239264
}
240265

241-
unsigned MipsCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {
242-
// this function will be automatically generated by the CodeEmitterGenerator
243-
// using TableGen
244-
return 0;
245-
}
266+
#include "MipsGenCodeEmitter.inc"

‎lib/Target/Mips/MipsInstrFPU.td

Lines changed: 35 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -76,14 +76,16 @@ def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
7676
// FP load.
7777
class FPLoad<bits<6> op, string opstr, PatFrag FOp, RegisterClass RC,
7878
Operand MemOpnd>:
79-
FFI<op, (outs RC:$ft), (ins MemOpnd:$base),
80-
!strconcat(opstr, "\t$ft, $base"), [(set RC:$ft, (FOp addr:$base))]>;
79+
FMem<op, (outs RC:$ft), (ins MemOpnd:$addr),
80+
!strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (FOp addr:$addr))],
81+
IILoad>;
8182

8283
// FP store.
8384
class FPStore<bits<6> op, string opstr, PatFrag FOp, RegisterClass RC,
8485
Operand MemOpnd>:
85-
FFI<op, (outs), (ins RC:$ft, MemOpnd:$base),
86-
!strconcat(opstr, "\t$ft, $base"), [(store RC:$ft, addr:$base)]>;
86+
FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr),
87+
!strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)],
88+
IIStore>;
8789

8890
// Instructions that convert an FP value to 32-bit fixed point.
8991
multiclass FFR1_W_M<bits<6> funct, string opstr> {
@@ -158,22 +160,28 @@ defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>;
158160
// stores, and moves between floating-point and integer registers.
159161
// When defining instructions, we reference all 32-bit registers,
160162
// regardless of register aliasing.
161-
let fd = 0 in {
162-
/// Move Control Registers From/To CPU Registers
163-
def CFC1 : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins CCR:$fs),
163+
164+
class FFRGPR<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern>:
165+
FFR<0x11, 0x0, _fmt, outs, ins, asmstr, pattern> {
166+
bits<5> rt;
167+
let ft = rt;
168+
let fd = 0;
169+
}
170+
171+
/// Move Control Registers From/To CPU Registers
172+
def CFC1 : FFRGPR<0x2, (outs CPURegs:$rt), (ins CCR:$fs),
164173
"cfc1\t$rt, $fs", []>;
165174

166-
def CTC1 : FFR<0x11, 0x0, 0x6, (outs CCR:$rt), (ins CPURegs:$fs),
167-
"ctc1\t$fs, $rt", []>;
175+
def CTC1 : FFRGPR<0x6, (outs CCR:$fs), (ins CPURegs:$rt),
176+
"ctc1\t$rt, $fs", []>;
168177

169-
def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
178+
def MFC1 : FFRGPR<0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
170179
"mfc1\t$rt, $fs",
171180
[(set CPURegs:$rt, (bitconvert FGR32:$fs))]>;
172181

173-
def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
182+
def MTC1 : FFRGPR<0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
174183
"mtc1\t$rt, $fs",
175184
[(set FGR32:$fs, (bitconvert CPURegs:$rt))]>;
176-
}
177185

178186
def FMOV_S : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>;
179187
def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>,
@@ -203,7 +211,7 @@ let Predicates = [NotN64] in {
203211
}
204212

205213
/// Floating-point Aritmetic
206-
defm FADD : FFR2P_M<0x10, "add", fadd, 1>;
214+
defm FADD : FFR2P_M<0x00, "add", fadd, 1>;
207215
defm FDIV : FFR2P_M<0x03, "div", fdiv>;
208216
defm FMUL : FFR2P_M<0x02, "mul", fmul, 1>;
209217
defm FSUB : FFR2P_M<0x01, "sub", fsub>;
@@ -218,12 +226,16 @@ def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
218226

219227
/// Floating Point Branch of False/True (Likely)
220228
let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in
221-
class FBRANCH<PatLeaf op, string asmstr> : FFI<0x11, (outs),
222-
(ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
223-
[(MipsFPBrcond op, bb:$dst)]>;
229+
class FBRANCH<bits<1> nd, bits<1> tf, PatLeaf op, string asmstr> :
230+
FFI<0x11, (outs), (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
231+
[(MipsFPBrcond op, bb:$dst)]> {
232+
let Inst{20-18} = 0;
233+
let Inst{17} = nd;
234+
let Inst{16} = tf;
235+
}
224236

225-
def BC1F : FBRANCH<MIPS_BRANCH_F, "bc1f">;
226-
def BC1T : FBRANCH<MIPS_BRANCH_T, "bc1t">;
237+
def BC1F : FBRANCH<0, 0, MIPS_BRANCH_F, "bc1f">;
238+
def BC1T : FBRANCH<0, 1, MIPS_BRANCH_T, "bc1t">;
227239

228240
//===----------------------------------------------------------------------===//
229241
// Floating Point Flag Conditions
@@ -249,11 +261,11 @@ def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
249261

250262
/// Floating Point Compare
251263
let Defs=[FCR31] in {
252-
def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
264+
def FCMP_S32 : FCC<0x10, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
253265
"c.$cc.s\t$fs, $ft",
254266
[(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>;
255267

256-
def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
268+
def FCMP_D32 : FCC<0x11, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
257269
"c.$cc.d\t$fs, $ft",
258270
[(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc)]>,
259271
Requires<[NotFP64bit]>;
@@ -287,14 +299,16 @@ let Predicates = [NotFP64bit] in {
287299
defm : MovnPats<AFGR64, MOVN_D>;
288300
}
289301

290-
let usesCustomInserter = 1, Uses = [FCR31], Constraints = "$F = $dst" in {
302+
let cc = 0, usesCustomInserter = 1, Uses = [FCR31],
303+
Constraints = "$F = $dst" in {
291304
// flag:float, data:int
292305
class CondMovFPInt<SDNode cmov, bits<1> tf, string instr_asm> :
293306
FCMOV<tf, (outs CPURegs:$dst), (ins CPURegs:$T, CPURegs:$F),
294307
!strconcat(instr_asm, "\t$dst, $T, $$fcc0"),
295308
[(set CPURegs:$dst, (cmov CPURegs:$T, CPURegs:$F))]>;
296309

297310
// flag:float, data:float
311+
let cc = 0 in
298312
class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf,
299313
string instr_asm> :
300314
FFCMOV<fmt, tf, (outs RC:$dst), (ins RC:$T, RC:$F),

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