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Merging r142350:
------------------------------------------------------------------------ r142350 | baldrick | 2011-10-18 05:44:00 -0700 (Tue, 18 Oct 2011) | 3 lines Fix a bunch of unused variable warnings when doing a release build with gcc-4.6. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@142609 91177308-0d34-0410-b5e6-96231b3b80d8
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+11
-11
lines changed

6 files changed

+11
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lines changed

‎lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -266,7 +266,6 @@ SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
266266
// Implement VSELECT in terms of XOR, AND, OR
267267
// on platforms which do not support blend natively.
268268
EVT VT = Op.getOperand(0).getValueType();
269-
EVT OVT = Op.getOperand(1).getValueType();
270269
DebugLoc DL = Op.getDebugLoc();
271270

272271
SDValue Mask = Op.getOperand(0);
@@ -280,7 +279,8 @@ SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
280279
!TLI.isOperationLegalOrCustom(ISD::OR, VT))
281280
return DAG.UnrollVectorOp(Op.getNode());
282281

283-
assert(VT.getSizeInBits() == OVT.getSizeInBits() && "Invalid mask size");
282+
assert(VT.getSizeInBits() == Op.getOperand(1).getValueType().getSizeInBits()
283+
&& "Invalid mask size");
284284
// Bitcast the operands to be the same type as the mask.
285285
// This is needed when we select between FP types because
286286
// the mask is a vector of integers.

‎lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2800,6 +2800,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
28002800
EVT.getVectorNumElements() == VT.getVectorNumElements()) &&
28012801
"Vector element counts must match in FP_ROUND_INREG");
28022802
assert(EVT.bitsLE(VT) && "Not rounding down!");
2803+
(void)EVT;
28032804
if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding.
28042805
break;
28052806
}

‎lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2474,7 +2474,7 @@ void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
24742474
size_t numCmps = Clusterify(Cases, SI);
24752475
DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
24762476
<< ". Total compares: " << numCmps << '\n');
2477-
numCmps = 0;
2477+
(void)numCmps;
24782478

24792479
// Get the Value to be switched on and default basic blocks, which will be
24802480
// inserted into CaseBlock records, representing basic blocks in the binary

‎lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4900,9 +4900,9 @@ static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
49004900
static void
49014901
ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results,
49024902
SelectionDAG &DAG, unsigned NewOp) {
4903-
EVT T = Node->getValueType(0);
49044903
DebugLoc dl = Node->getDebugLoc();
4905-
assert (T == MVT::i64 && "Only know how to expand i64 atomics");
4904+
assert (Node->getValueType(0) == MVT::i64 &&
4905+
"Only know how to expand i64 atomics");
49064906

49074907
SmallVector<SDValue, 6> Ops;
49084908
Ops.push_back(Node->getOperand(0)); // Chain

‎lib/Target/X86/X86FrameLowering.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1113,9 +1113,7 @@ int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) con
11131113
// Skip the saved EBP.
11141114
Offset += RI->getSlotSize();
11151115
} else {
1116-
unsigned Align = MFI->getObjectAlignment(FI);
1117-
assert((-(Offset + StackSize)) % Align == 0);
1118-
Align = 0;
1116+
assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
11191117
return Offset + StackSize;
11201118
}
11211119
// FIXME: Support tail calls
@@ -1267,7 +1265,7 @@ X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
12671265
true);
12681266
assert(FrameIdx == MFI->getObjectIndexBegin() &&
12691267
"Slot for EBP register must be last in order to be found!");
1270-
FrameIdx = 0;
1268+
(void)FrameIdx;
12711269
}
12721270
}
12731271

‎lib/Target/X86/X86ISelLowering.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1753,6 +1753,7 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
17531753
// places.
17541754
assert(VA.getValNo() != LastVal &&
17551755
"Don't support value assigned to multiple locs yet");
1756+
(void)LastVal;
17561757
LastVal = VA.getValNo();
17571758

17581759
if (VA.isRegLoc()) {
@@ -10477,9 +10478,9 @@ static void ReplaceATOMIC_LOAD(SDNode *Node,
1047710478
void X86TargetLowering::
1047810479
ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
1047910480
SelectionDAG &DAG, unsigned NewOp) const {
10480-
EVT T = Node->getValueType(0);
1048110481
DebugLoc dl = Node->getDebugLoc();
10482-
assert (T == MVT::i64 && "Only know how to expand i64 atomics");
10482+
assert (Node->getValueType(0) == MVT::i64 &&
10483+
"Only know how to expand i64 atomics");
1048310484

1048410485
SDValue Chain = Node->getOperand(0);
1048510486
SDValue In1 = Node->getOperand(1);

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