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[ARM] Add and adjust saturation tests for upcoming qadd changes. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375401 91177308-0d34-0410-b5e6-96231b3b80d8
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‎test/CodeGen/ARM/qdadd.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
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; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
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; RUN: llc < %s -mtriple=armv5te-none-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARM6
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; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARM8
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define i32 @qdadd(i32 %x, i32 %y) nounwind {
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; CHECK-T2-LABEL: qdadd:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: .save {r7, lr}
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; CHECK-T2-NEXT: push {r7, lr}
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; CHECK-T2-NEXT: movs r3, #0
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; CHECK-T2-NEXT: adds.w r12, r0, r0
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi r3, #1
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; CHECK-T2-NEXT: cmp r3, #0
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; CHECK-T2-NEXT: mov.w r3, #-2147483648
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; CHECK-T2-NEXT: mov.w lr, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r3, #-2147483648
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; CHECK-T2-NEXT: cmp r12, r0
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r3, r12
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; CHECK-T2-NEXT: adds r0, r3, r1
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; CHECK-T2-NEXT: mov.w r2, #-2147483648
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi.w lr, #1
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; CHECK-T2-NEXT: cmp.w lr, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r2, #-2147483648
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; CHECK-T2-NEXT: cmp r0, r3
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r2, r0
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; CHECK-T2-NEXT: mov r0, r2
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; CHECK-T2-NEXT: pop {r7, pc}
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;
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; CHECK-ARM6-LABEL: qdadd:
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; CHECK-ARM6: @ %bb.0:
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; CHECK-ARM6-NEXT: .save {r11, lr}
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; CHECK-ARM6-NEXT: push {r11, lr}
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; CHECK-ARM6-NEXT: adds r12, r0, r0
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; CHECK-ARM6-NEXT: mov r3, #0
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; CHECK-ARM6-NEXT: movmi r3, #1
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; CHECK-ARM6-NEXT: cmp r3, #0
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; CHECK-ARM6-NEXT: mov r3, #-2147483648
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; CHECK-ARM6-NEXT: mov lr, #0
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; CHECK-ARM6-NEXT: mvnne r3, #-2147483648
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; CHECK-ARM6-NEXT: cmp r12, r0
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; CHECK-ARM6-NEXT: movvc r3, r12
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; CHECK-ARM6-NEXT: adds r0, r3, r1
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; CHECK-ARM6-NEXT: movmi lr, #1
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; CHECK-ARM6-NEXT: mov r2, #-2147483648
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; CHECK-ARM6-NEXT: cmp lr, #0
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; CHECK-ARM6-NEXT: mvnne r2, #-2147483648
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; CHECK-ARM6-NEXT: cmp r0, r3
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; CHECK-ARM6-NEXT: movvc r2, r0
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; CHECK-ARM6-NEXT: mov r0, r2
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; CHECK-ARM6-NEXT: pop {r11, pc}
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;
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; CHECK-ARM8-LABEL: qdadd:
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; CHECK-ARM8: @ %bb.0:
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; CHECK-ARM8-NEXT: .save {r11, lr}
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; CHECK-ARM8-NEXT: push {r11, lr}
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; CHECK-ARM8-NEXT: adds r12, r0, r0
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; CHECK-ARM8-NEXT: mov r3, #0
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; CHECK-ARM8-NEXT: movwmi r3, #1
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; CHECK-ARM8-NEXT: cmp r3, #0
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; CHECK-ARM8-NEXT: mov r3, #-2147483648
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; CHECK-ARM8-NEXT: mov lr, #0
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; CHECK-ARM8-NEXT: mvnne r3, #-2147483648
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; CHECK-ARM8-NEXT: cmp r12, r0
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; CHECK-ARM8-NEXT: movvc r3, r12
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; CHECK-ARM8-NEXT: adds r0, r3, r1
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; CHECK-ARM8-NEXT: movwmi lr, #1
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; CHECK-ARM8-NEXT: mov r2, #-2147483648
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; CHECK-ARM8-NEXT: cmp lr, #0
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; CHECK-ARM8-NEXT: mvnne r2, #-2147483648
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; CHECK-ARM8-NEXT: cmp r0, r3
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; CHECK-ARM8-NEXT: movvc r2, r0
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; CHECK-ARM8-NEXT: mov r0, r2
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; CHECK-ARM8-NEXT: pop {r11, pc}
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%z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
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%tmp = call i32 @llvm.sadd.sat.i32(i32 %z, i32 %y)
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ret i32 %tmp
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}
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define i32 @qdadd_c(i32 %x, i32 %y) nounwind {
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; CHECK-T2-LABEL: qdadd_c:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: .save {r7, lr}
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; CHECK-T2-NEXT: push {r7, lr}
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; CHECK-T2-NEXT: movs r3, #0
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; CHECK-T2-NEXT: adds.w r12, r0, r0
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi r3, #1
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; CHECK-T2-NEXT: cmp r3, #0
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; CHECK-T2-NEXT: mov.w r3, #-2147483648
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; CHECK-T2-NEXT: mov.w lr, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r3, #-2147483648
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; CHECK-T2-NEXT: cmp r12, r0
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r3, r12
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; CHECK-T2-NEXT: adds r0, r1, r3
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; CHECK-T2-NEXT: mov.w r2, #-2147483648
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi.w lr, #1
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; CHECK-T2-NEXT: cmp.w lr, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r2, #-2147483648
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; CHECK-T2-NEXT: cmp r0, r1
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r2, r0
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; CHECK-T2-NEXT: mov r0, r2
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; CHECK-T2-NEXT: pop {r7, pc}
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;
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; CHECK-ARM6-LABEL: qdadd_c:
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; CHECK-ARM6: @ %bb.0:
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; CHECK-ARM6-NEXT: .save {r11, lr}
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; CHECK-ARM6-NEXT: push {r11, lr}
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; CHECK-ARM6-NEXT: adds r12, r0, r0
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; CHECK-ARM6-NEXT: mov r3, #0
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; CHECK-ARM6-NEXT: movmi r3, #1
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; CHECK-ARM6-NEXT: cmp r3, #0
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; CHECK-ARM6-NEXT: mov r3, #-2147483648
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; CHECK-ARM6-NEXT: mov lr, #0
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; CHECK-ARM6-NEXT: mvnne r3, #-2147483648
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; CHECK-ARM6-NEXT: cmp r12, r0
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; CHECK-ARM6-NEXT: movvc r3, r12
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; CHECK-ARM6-NEXT: adds r0, r1, r3
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; CHECK-ARM6-NEXT: movmi lr, #1
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; CHECK-ARM6-NEXT: mov r2, #-2147483648
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; CHECK-ARM6-NEXT: cmp lr, #0
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; CHECK-ARM6-NEXT: mvnne r2, #-2147483648
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; CHECK-ARM6-NEXT: cmp r0, r1
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; CHECK-ARM6-NEXT: movvc r2, r0
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; CHECK-ARM6-NEXT: mov r0, r2
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; CHECK-ARM6-NEXT: pop {r11, pc}
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;
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; CHECK-ARM8-LABEL: qdadd_c:
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; CHECK-ARM8: @ %bb.0:
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; CHECK-ARM8-NEXT: .save {r11, lr}
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; CHECK-ARM8-NEXT: push {r11, lr}
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; CHECK-ARM8-NEXT: adds r12, r0, r0
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; CHECK-ARM8-NEXT: mov r3, #0
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; CHECK-ARM8-NEXT: movwmi r3, #1
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; CHECK-ARM8-NEXT: cmp r3, #0
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; CHECK-ARM8-NEXT: mov r3, #-2147483648
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; CHECK-ARM8-NEXT: mov lr, #0
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; CHECK-ARM8-NEXT: mvnne r3, #-2147483648
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; CHECK-ARM8-NEXT: cmp r12, r0
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; CHECK-ARM8-NEXT: movvc r3, r12
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; CHECK-ARM8-NEXT: adds r0, r1, r3
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; CHECK-ARM8-NEXT: movwmi lr, #1
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; CHECK-ARM8-NEXT: mov r2, #-2147483648
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; CHECK-ARM8-NEXT: cmp lr, #0
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; CHECK-ARM8-NEXT: mvnne r2, #-2147483648
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; CHECK-ARM8-NEXT: cmp r0, r1
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; CHECK-ARM8-NEXT: movvc r2, r0
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; CHECK-ARM8-NEXT: mov r0, r2
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; CHECK-ARM8-NEXT: pop {r11, pc}
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%z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
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%tmp = call i32 @llvm.sadd.sat.i32(i32 %y, i32 %z)
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ret i32 %tmp
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}
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define i32 @qdsub(i32 %x, i32 %y) nounwind {
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; CHECK-T2-LABEL: qdsub:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: .save {r7, lr}
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; CHECK-T2-NEXT: push {r7, lr}
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; CHECK-T2-NEXT: movs r3, #0
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; CHECK-T2-NEXT: adds.w r12, r0, r0
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi r3, #1
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; CHECK-T2-NEXT: cmp r3, #0
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; CHECK-T2-NEXT: mov.w r3, #-2147483648
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; CHECK-T2-NEXT: mov.w lr, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r3, #-2147483648
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; CHECK-T2-NEXT: cmp r12, r0
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r3, r12
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; CHECK-T2-NEXT: subs r0, r1, r3
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; CHECK-T2-NEXT: mov.w r2, #-2147483648
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi.w lr, #1
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; CHECK-T2-NEXT: cmp.w lr, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r2, #-2147483648
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; CHECK-T2-NEXT: cmp r1, r3
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r2, r0
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; CHECK-T2-NEXT: mov r0, r2
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; CHECK-T2-NEXT: pop {r7, pc}
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;
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; CHECK-ARM6-LABEL: qdsub:
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; CHECK-ARM6: @ %bb.0:
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; CHECK-ARM6-NEXT: .save {r11, lr}
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; CHECK-ARM6-NEXT: push {r11, lr}
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; CHECK-ARM6-NEXT: adds r12, r0, r0
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; CHECK-ARM6-NEXT: mov r3, #0
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; CHECK-ARM6-NEXT: movmi r3, #1
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; CHECK-ARM6-NEXT: cmp r3, #0
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; CHECK-ARM6-NEXT: mov r3, #-2147483648
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; CHECK-ARM6-NEXT: mov lr, #0
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; CHECK-ARM6-NEXT: mvnne r3, #-2147483648
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; CHECK-ARM6-NEXT: cmp r12, r0
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; CHECK-ARM6-NEXT: movvc r3, r12
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; CHECK-ARM6-NEXT: subs r0, r1, r3
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; CHECK-ARM6-NEXT: movmi lr, #1
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; CHECK-ARM6-NEXT: mov r2, #-2147483648
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; CHECK-ARM6-NEXT: cmp lr, #0
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; CHECK-ARM6-NEXT: mvnne r2, #-2147483648
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; CHECK-ARM6-NEXT: cmp r1, r3
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; CHECK-ARM6-NEXT: movvc r2, r0
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; CHECK-ARM6-NEXT: mov r0, r2
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; CHECK-ARM6-NEXT: pop {r11, pc}
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;
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; CHECK-ARM8-LABEL: qdsub:
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; CHECK-ARM8: @ %bb.0:
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; CHECK-ARM8-NEXT: .save {r11, lr}
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; CHECK-ARM8-NEXT: push {r11, lr}
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; CHECK-ARM8-NEXT: adds r12, r0, r0
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; CHECK-ARM8-NEXT: mov r3, #0
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; CHECK-ARM8-NEXT: movwmi r3, #1
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; CHECK-ARM8-NEXT: cmp r3, #0
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; CHECK-ARM8-NEXT: mov r3, #-2147483648
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; CHECK-ARM8-NEXT: mov lr, #0
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; CHECK-ARM8-NEXT: mvnne r3, #-2147483648
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; CHECK-ARM8-NEXT: cmp r12, r0
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; CHECK-ARM8-NEXT: movvc r3, r12
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; CHECK-ARM8-NEXT: subs r0, r1, r3
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; CHECK-ARM8-NEXT: movwmi lr, #1
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; CHECK-ARM8-NEXT: mov r2, #-2147483648
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; CHECK-ARM8-NEXT: cmp lr, #0
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; CHECK-ARM8-NEXT: mvnne r2, #-2147483648
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; CHECK-ARM8-NEXT: cmp r1, r3
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; CHECK-ARM8-NEXT: movvc r2, r0
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; CHECK-ARM8-NEXT: mov r0, r2
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; CHECK-ARM8-NEXT: pop {r11, pc}
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%z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
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%tmp = call i32 @llvm.ssub.sat.i32(i32 %y, i32 %z)
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ret i32 %tmp
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}
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define i32 @qdsub_c(i32 %x, i32 %y) nounwind {
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; CHECK-T2-LABEL: qdsub_c:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: .save {r7, lr}
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; CHECK-T2-NEXT: push {r7, lr}
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; CHECK-T2-NEXT: movs r3, #0
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; CHECK-T2-NEXT: adds.w r12, r0, r0
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi r3, #1
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; CHECK-T2-NEXT: cmp r3, #0
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; CHECK-T2-NEXT: mov.w r3, #-2147483648
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; CHECK-T2-NEXT: mov.w lr, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r3, #-2147483648
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; CHECK-T2-NEXT: cmp r12, r0
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r3, r12
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; CHECK-T2-NEXT: subs r0, r3, r1
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; CHECK-T2-NEXT: mov.w r2, #-2147483648
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi.w lr, #1
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; CHECK-T2-NEXT: cmp.w lr, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r2, #-2147483648
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; CHECK-T2-NEXT: cmp r3, r1
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r2, r0
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; CHECK-T2-NEXT: mov r0, r2
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; CHECK-T2-NEXT: pop {r7, pc}
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;
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; CHECK-ARM6-LABEL: qdsub_c:
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; CHECK-ARM6: @ %bb.0:
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; CHECK-ARM6-NEXT: .save {r11, lr}
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; CHECK-ARM6-NEXT: push {r11, lr}
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; CHECK-ARM6-NEXT: adds r12, r0, r0
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; CHECK-ARM6-NEXT: mov r3, #0
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; CHECK-ARM6-NEXT: movmi r3, #1
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; CHECK-ARM6-NEXT: cmp r3, #0
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; CHECK-ARM6-NEXT: mov r3, #-2147483648
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; CHECK-ARM6-NEXT: mov lr, #0
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; CHECK-ARM6-NEXT: mvnne r3, #-2147483648
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; CHECK-ARM6-NEXT: cmp r12, r0
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; CHECK-ARM6-NEXT: movvc r3, r12
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; CHECK-ARM6-NEXT: subs r0, r3, r1
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; CHECK-ARM6-NEXT: movmi lr, #1
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; CHECK-ARM6-NEXT: mov r2, #-2147483648
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; CHECK-ARM6-NEXT: cmp lr, #0
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; CHECK-ARM6-NEXT: mvnne r2, #-2147483648
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; CHECK-ARM6-NEXT: cmp r3, r1
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; CHECK-ARM6-NEXT: movvc r2, r0
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; CHECK-ARM6-NEXT: mov r0, r2
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; CHECK-ARM6-NEXT: pop {r11, pc}
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;
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; CHECK-ARM8-LABEL: qdsub_c:
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; CHECK-ARM8: @ %bb.0:
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; CHECK-ARM8-NEXT: .save {r11, lr}
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; CHECK-ARM8-NEXT: push {r11, lr}
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; CHECK-ARM8-NEXT: adds r12, r0, r0
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; CHECK-ARM8-NEXT: mov r3, #0
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; CHECK-ARM8-NEXT: movwmi r3, #1
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; CHECK-ARM8-NEXT: cmp r3, #0
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; CHECK-ARM8-NEXT: mov r3, #-2147483648
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; CHECK-ARM8-NEXT: mov lr, #0
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; CHECK-ARM8-NEXT: mvnne r3, #-2147483648
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; CHECK-ARM8-NEXT: cmp r12, r0
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; CHECK-ARM8-NEXT: movvc r3, r12
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; CHECK-ARM8-NEXT: subs r0, r3, r1
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; CHECK-ARM8-NEXT: movwmi lr, #1
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; CHECK-ARM8-NEXT: mov r2, #-2147483648
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; CHECK-ARM8-NEXT: cmp lr, #0
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; CHECK-ARM8-NEXT: mvnne r2, #-2147483648
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; CHECK-ARM8-NEXT: cmp r3, r1
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; CHECK-ARM8-NEXT: movvc r2, r0
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; CHECK-ARM8-NEXT: mov r0, r2
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; CHECK-ARM8-NEXT: pop {r11, pc}
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%z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
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%tmp = call i32 @llvm.ssub.sat.i32(i32 %z, i32 %y)
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ret i32 %tmp
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}
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declare i32 @llvm.sadd.sat.i32(i32, i32)
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declare i32 @llvm.ssub.sat.i32(i32, i32)

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