Merging r314252:

tstellar · tstellar · commit b5ef7376bc13 · 2017-09-29T20:35:06.000Z
------------------------------------------------------------------------ r314252 | gberry | 2017-09-26 14:40:46 -0700 (Tue, 26 Sep 2017) | 12 lines [AArch64][Falkor] Fix bug in falkor prefetcher fix pass. Summary: In rare cases, loads that don't get prefetched that were marked as strided loads could cause a crash if they occurred in a loop with other colliding loads. Reviewers: mcrosier Subscribers: aemerson, rengolin, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D38261 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314555 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp b/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
@@ -690,9 +690,14 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineFunction &Fn) {
       if (!TII->isStridedAccess(MI))
         continue;
 
-      LoadInfo LdI = *getLoadInfo(MI);
-      unsigned OldTag = *getTag(TRI, MI, LdI);
-      auto &OldCollisions = TagMap[OldTag];
+      Optional<LoadInfo> OptLdI = getLoadInfo(MI);
+      if (!OptLdI)
+        continue;
+      LoadInfo LdI = *OptLdI;
+      Optional<unsigned> OptOldTag = getTag(TRI, MI, LdI);
+      if (!OptOldTag)
+        continue;
+      auto &OldCollisions = TagMap[*OptOldTag];
       if (OldCollisions.size() <= 1)
         continue;
 
diff --git a/test/CodeGen/AArch64/falkor-hwpf-fix.mir b/test/CodeGen/AArch64/falkor-hwpf-fix.mir
@@ -305,3 +305,28 @@ body: |
   bb.1:
     RET_ReallyLR
 ...
+---
+# Check that we handle case of strided load with no HW prefetcher tag correctly.
+
+# CHECK-LABEL: name: hwpf_notagbug
+# CHECK-NOT: ORRXrs %xzr
+# CHECK: LDARW %x1
+# CHECK-NOT: ORRXrs %xzr
+# CHECK: LDRWui %x1
+name:            hwpf_notagbug
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: %w0, %x1, %x17
+
+    %w1 = LDARW %x1 :: ("aarch64-strided-access" load 4)
+    %w1 = LDRWui %x1, 0 :: ("aarch64-strided-access" load 4)
+    %w17 = LDRWui %x17, 0 :: ("aarch64-strided-access" load 4)
+
+    %w0 = SUBWri %w0, 1, 0
+    %wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
+    Bcc 9, %bb.0, implicit %nzcv
+
+  bb.1:
+    RET_ReallyLR
+...
