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tstellartstellar
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[9.0 branch][ARM] VFPv2 only supports 16 D registers.
Summary: Patch for 9.0.1. Simplified version of r372186/r372187: fix the meaning of the "vfpv2" and "vfpv2sp" features, but keep around the useless "vfp2d16" and "vfp2d16sp" features, to reduce the risk on the release branch. Fixes https://bugs.llvm.org/show_bug.cgi?id=43365 Reviewers: t.p.northover, tstellar Reviewed By: t.p.northover Subscribers: kristof.beyls, hiraditya, kristina, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68675 llvm-svn: 374433
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‎clang/test/CodeGen/arm-target-features.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -38,24 +38,24 @@
3838
// CHECK-BASIC-V8-ARM: "target-features"="+armv8-a,+crc,+crypto,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+fpregs,+hwdiv,+hwdiv-arm,+neon,+vfp2,+vfp2d16,+vfp2d16sp,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp,-thumb-mode"
3939

4040
// RUN: %clang_cc1 -triple thumbv7-linux-gnueabi -target-cpu cortex-r5 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-VFP3-D16-DIV
41-
// CHECK-VFP3-D16-DIV: "target-features"="+armv7-r,+dsp,+fp64,+fpregs,+hwdiv,+hwdiv-arm,+thumb-mode,+vfp2d16,+vfp2d16sp,+vfp3d16,+vfp3d16sp"
41+
// CHECK-VFP3-D16-DIV: "target-features"="+armv7-r,+dsp,+fp64,+fpregs,+hwdiv,+hwdiv-arm,+thumb-mode,+vfp2,+vfp2d16,+vfp2d16sp,+vfp2sp,+vfp3d16,+vfp3d16sp"
4242

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4444
// RUN: %clang_cc1 -triple armv7-linux-gnueabi -target-cpu cortex-r4f -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-VFP3-D16-THUMB-DIV
45-
// CHECK-VFP3-D16-THUMB-DIV: "target-features"="+armv7-r,+dsp,+fp64,+fpregs,+hwdiv,+vfp2d16,+vfp2d16sp,+vfp3d16,+vfp3d16sp,-thumb-mode"
45+
// CHECK-VFP3-D16-THUMB-DIV: "target-features"="+armv7-r,+dsp,+fp64,+fpregs,+hwdiv,+vfp2,+vfp2d16,+vfp2d16sp,+vfp2sp,+vfp3d16,+vfp3d16sp,-thumb-mode"
4646

4747

4848
// RUN: %clang_cc1 -triple thumbv7-linux-gnueabi -target-cpu cortex-r7 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-VFP3-D16-FP16-DIV
4949
// RUN: %clang_cc1 -triple thumbv7-linux-gnueabi -target-cpu cortex-r8 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-VFP3-D16-FP16-DIV
50-
// CHECK-VFP3-D16-FP16-DIV: "target-features"="+armv7-r,+dsp,+fp16,+fp64,+fpregs,+hwdiv,+hwdiv-arm,+thumb-mode,+vfp2d16,+vfp2d16sp,+vfp3d16,+vfp3d16sp"
50+
// CHECK-VFP3-D16-FP16-DIV: "target-features"="+armv7-r,+dsp,+fp16,+fp64,+fpregs,+hwdiv,+hwdiv-arm,+thumb-mode,+vfp2,+vfp2d16,+vfp2d16sp,+vfp2sp,+vfp3d16,+vfp3d16sp"
5151

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5353
// RUN: %clang_cc1 -triple thumbv7-linux-gnueabi -target-cpu cortex-m4 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-VFP4-D16-SP-THUMB-DIV
54-
// CHECK-VFP4-D16-SP-THUMB-DIV: "target-features"="+armv7e-m,+dsp,+fp16,+fpregs,+hwdiv,+thumb-mode,+vfp2d16sp,+vfp3d16sp,+vfp4d16sp"
54+
// CHECK-VFP4-D16-SP-THUMB-DIV: "target-features"="+armv7e-m,+dsp,+fp16,+fpregs,+hwdiv,+thumb-mode,+vfp2d16sp,+vfp2sp,+vfp3d16sp,+vfp4d16sp"
5555

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5757
// RUN: %clang_cc1 -triple thumbv7-linux-gnueabi -target-cpu cortex-m7 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-VFP5-D16-THUMB-DIV
58-
// CHECK-VFP5-D16-THUMB-DIV: "target-features"="+armv7e-m,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fpregs,+hwdiv,+thumb-mode,+vfp2d16,+vfp2d16sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
58+
// CHECK-VFP5-D16-THUMB-DIV: "target-features"="+armv7e-m,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fpregs,+hwdiv,+thumb-mode,+vfp2,+vfp2d16,+vfp2d16sp,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
5959

6060

6161
// RUN: %clang_cc1 -triple armv7-linux-gnueabi -target-cpu cortex-r4 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-THUMB-DIV
@@ -107,6 +107,6 @@
107107
// CHECK-ARMV8M-M23-LINUX: "target-features"="+armv8-m.base,+hwdiv,+thumb-mode"
108108

109109
// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m33 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV8M-MAIN-LINUX
110-
// CHECK-ARMV8M-MAIN-LINUX: "target-features"="+armv8-m.main,+dsp,+fp-armv8d16sp,+fp16,+fpregs,+hwdiv,+thumb-mode,+vfp2d16sp,+vfp3d16sp,+vfp4d16sp"
110+
// CHECK-ARMV8M-MAIN-LINUX: "target-features"="+armv8-m.main,+dsp,+fp-armv8d16sp,+fp16,+fpregs,+hwdiv,+thumb-mode,+vfp2d16sp,+vfp2sp,+vfp3d16sp,+vfp4d16sp"
111111

112112
void foo() {}

‎llvm/lib/Support/ARMTargetParser.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -176,10 +176,10 @@ bool ARM::getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features) {
176176
// exist).
177177

178178
{"+fpregs", "-fpregs", FPUVersion::VFPV2, FPURestriction::SP_D16},
179-
{"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::None},
179+
{"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::D16},
180180
{"+vfp2d16", "-vfp2d16", FPUVersion::VFPV2, FPURestriction::D16},
181181
{"+vfp2d16sp", "-vfp2d16sp", FPUVersion::VFPV2, FPURestriction::SP_D16},
182-
{"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::None},
182+
{"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::SP_D16},
183183
{"+vfp3", "-vfp3", FPUVersion::VFPV3, FPURestriction::None},
184184
{"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16},
185185
{"+vfp3d16sp", "-vfp3d16sp", FPUVersion::VFPV3, FPURestriction::SP_D16},
@@ -195,7 +195,7 @@ bool ARM::getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features) {
195195
{"+fp-armv8sp", "-fp-armv8sp", FPUVersion::VFPV5, FPURestriction::None},
196196
{"+fullfp16", "-fullfp16", FPUVersion::VFPV5_FULLFP16, FPURestriction::SP_D16},
197197
{"+fp64", "-fp64", FPUVersion::VFPV2, FPURestriction::D16},
198-
{"+d32", "-d32", FPUVersion::VFPV2, FPURestriction::None},
198+
{"+d32", "-d32", FPUVersion::VFPV3, FPURestriction::None},
199199
};
200200

201201
for (const auto &Info: FPUFeatureInfoList) {

‎llvm/lib/Target/ARM/ARM.td

Lines changed: 23 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -57,12 +57,15 @@ def FeatureD32 : SubtargetFeature<"d32", "HasD32", "true",
5757
"Extend FP to 32 double registers">;
5858

5959
multiclass VFPver<string name, string query, string description,
60-
list<SubtargetFeature> prev = [],
61-
list<SubtargetFeature> otherimplies = []> {
60+
list<SubtargetFeature> prev,
61+
list<SubtargetFeature> otherimplies,
62+
list<SubtargetFeature> vfp2prev = []> {
6263
def _D16_SP: SubtargetFeature<
6364
name#"d16sp", query#"D16SP", "true",
6465
description#" with only 16 d-registers and no double precision",
65-
!foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) # otherimplies>;
66+
!foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) #
67+
!foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) #
68+
otherimplies>;
6669
def _SP: SubtargetFeature<
6770
name#"sp", query#"SP", "true",
6871
description#" with no double precision",
@@ -72,6 +75,7 @@ multiclass VFPver<string name, string query, string description,
7275
name#"d16", query#"D16", "true",
7376
description#" with only 16 d-registers",
7477
!foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) #
78+
vfp2prev #
7579
otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>;
7680
def "": SubtargetFeature<
7781
name, query, "true", description,
@@ -80,11 +84,23 @@ multiclass VFPver<string name, string query, string description,
8084
!cast<SubtargetFeature>(NAME # "_SP")]>;
8185
}
8286

83-
defm FeatureVFP2: VFPver<"vfp2", "HasVFPv2", "Enable VFP2 instructions",
84-
[], [FeatureFPRegs]>;
87+
def FeatureVFP2_D16_SP : SubtargetFeature<"vfp2d16sp", "HasVFPv2D16SP", "true",
88+
"Enable VFP2 instructions with "
89+
"no double precision",
90+
[FeatureFPRegs]>;
91+
def FeatureVFP2_SP : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true",
92+
"Enable VFP2 instructions with "
93+
"no double precision",
94+
[FeatureVFP2_D16_SP]>;
95+
def FeatureVFP2_D16 : SubtargetFeature<"vfp2d16", "HasVFPv2D16", "true",
96+
"Enable VFP2 instructions",
97+
[FeatureFP64, FeatureVFP2_D16_SP]>;
98+
def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
99+
"Enable VFP2 instructions",
100+
[FeatureVFP2_D16, FeatureVFP2_SP]>;
85101

86102
defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions",
87-
[FeatureVFP2]>;
103+
[], [], [FeatureVFP2]>;
88104

89105
def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
90106
"Enable NEON instructions",
@@ -98,7 +114,7 @@ defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions",
98114
[FeatureVFP3], [FeatureFP16]>;
99115

100116
defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP",
101-
[FeatureVFP4]>;
117+
[FeatureVFP4], []>;
102118

103119
def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
104120
"Enable full half-precision "

‎llvm/test/MC/ARM/vfp-aliases-diagnostics.s

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -13,34 +13,34 @@ aliases:
1313
fldmeax sp!, {s0}
1414

1515
@ CHECK-LABEL: aliases
16-
@ CHECK: error: operand must be a list of registers in range [d0, d31]
16+
@ CHECK: error: operand must be a list of registers in range [d0, d15]
1717
@ CHECK: fstmeax sp!, {s0}
1818
@ CHECK: ^
19-
@ CHECK: error: operand must be a list of registers in range [d0, d31]
19+
@ CHECK: error: operand must be a list of registers in range [d0, d15]
2020
@ CHECK: fldmfdx sp!, {s0}
2121
@ CHECK: ^
2222

23-
@ CHECK: error: operand must be a list of registers in range [d0, d31]
23+
@ CHECK: error: operand must be a list of registers in range [d0, d15]
2424
@ CHECK: fstmfdx sp!, {s0}
2525
@ CHECK: ^
26-
@ CHECK: error: operand must be a list of registers in range [d0, d31]
26+
@ CHECK: error: operand must be a list of registers in range [d0, d15]
2727
@ CHECK: fldmeax sp!, {s0}
2828
@ CHECK: ^
2929

3030
fstmiaxcs r0, {s0}
3131
fstmiaxhs r0, {s0}
3232
fstmiaxls r0, {s0}
3333
fstmiaxvs r0, {s0}
34-
@ CHECK: error: operand must be a list of registers in range [d0, d31]
34+
@ CHECK: error: operand must be a list of registers in range [d0, d15]
3535
@ CHECK: fstmiaxcs r0, {s0}
3636
@ CHECK: ^
37-
@ CHECK: error: operand must be a list of registers in range [d0, d31]
37+
@ CHECK: error: operand must be a list of registers in range [d0, d15]
3838
@ CHECK: fstmiaxhs r0, {s0}
3939
@ CHECK: ^
40-
@ CHECK: error: operand must be a list of registers in range [d0, d31]
40+
@ CHECK: error: operand must be a list of registers in range [d0, d15]
4141
@ CHECK: fstmiaxls r0, {s0}
4242
@ CHECK: ^
43-
@ CHECK: error: operand must be a list of registers in range [d0, d31]
43+
@ CHECK: error: operand must be a list of registers in range [d0, d15]
4444
@ CHECK: fstmiaxvs r0, {s0}
4545
@ CHECK: ^
4646

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