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kaz7Simon Moll
kaz7
authored and
Simon Moll
committed
[VE] Update branch instructions
Summary: Changing all mnemonic to match assembly instructions to simplify mnemonic naming rules. This time update all branch instructions. This also change to use %s10 register consistently. Differential Revision: https://reviews.llvm.org/D78889
1 parent 0314e89 commit 3c80478

12 files changed

+294
-230
lines changed

‎llvm/lib/Target/VE/VEAsmPrinter.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -88,9 +88,12 @@ static void emitSIC(MCStreamer &OutStreamer, MCOperand &RD,
8888
static void emitBSIC(MCStreamer &OutStreamer, MCOperand &R1, MCOperand &R2,
8989
const MCSubtargetInfo &STI) {
9090
MCInst BSICInst;
91-
BSICInst.setOpcode(VE::BSIC);
91+
BSICInst.setOpcode(VE::BSICrii);
9292
BSICInst.addOperand(R1);
9393
BSICInst.addOperand(R2);
94+
MCOperand czero = MCOperand::createImm(0);
95+
BSICInst.addOperand(czero);
96+
BSICInst.addOperand(czero);
9497
OutStreamer.emitInstruction(BSICInst, STI);
9598
}
9699

‎llvm/lib/Target/VE/VEInstrInfo.cpp

Lines changed: 47 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -68,25 +68,38 @@ static VECC::CondCode GetOppositeBranchCondition(VECC::CondCode CC) {
6868
llvm_unreachable("Invalid cond code");
6969
}
7070

71-
// Treat br.l [BCR AT] as unconditional branch
71+
// Treat br.l [BRCF AT] as unconditional branch
7272
static bool isUncondBranchOpcode(int Opc) {
73-
return Opc == VE::BCRLa || Opc == VE::BCRWa ||
74-
Opc == VE::BCRDa || Opc == VE::BCRSa;
73+
return Opc == VE::BRCFLa || Opc == VE::BRCFWa ||
74+
Opc == VE::BRCFLa_nt || Opc == VE::BRCFWa_nt ||
75+
Opc == VE::BRCFLa_t || Opc == VE::BRCFWa_t ||
76+
Opc == VE::BRCFDa || Opc == VE::BRCFSa ||
77+
Opc == VE::BRCFDa_nt || Opc == VE::BRCFSa_nt ||
78+
Opc == VE::BRCFDa_t || Opc == VE::BRCFSa_t;
7579
}
7680

7781
static bool isCondBranchOpcode(int Opc) {
78-
return Opc == VE::BCRLrr || Opc == VE::BCRLir ||
79-
Opc == VE::BCRLrm0 || Opc == VE::BCRLrm1 ||
80-
Opc == VE::BCRLim0 || Opc == VE::BCRLim1 ||
81-
Opc == VE::BCRWrr || Opc == VE::BCRWir ||
82-
Opc == VE::BCRWrm0 || Opc == VE::BCRWrm1 ||
83-
Opc == VE::BCRWim0 || Opc == VE::BCRWim1 ||
84-
Opc == VE::BCRDrr || Opc == VE::BCRDir ||
85-
Opc == VE::BCRDrm0 || Opc == VE::BCRDrm1 ||
86-
Opc == VE::BCRDim0 || Opc == VE::BCRDim1 ||
87-
Opc == VE::BCRSrr || Opc == VE::BCRSir ||
88-
Opc == VE::BCRSrm0 || Opc == VE::BCRSrm1 ||
89-
Opc == VE::BCRSim0 || Opc == VE::BCRSim1;
82+
return Opc == VE::BRCFLrr || Opc == VE::BRCFLir ||
83+
Opc == VE::BRCFLrr_nt || Opc == VE::BRCFLir_nt ||
84+
Opc == VE::BRCFLrr_t || Opc == VE::BRCFLir_t ||
85+
Opc == VE::BRCFWrr || Opc == VE::BRCFWir ||
86+
Opc == VE::BRCFWrr_nt || Opc == VE::BRCFWir_nt ||
87+
Opc == VE::BRCFWrr_t || Opc == VE::BRCFWir_t ||
88+
Opc == VE::BRCFDrr || Opc == VE::BRCFDir ||
89+
Opc == VE::BRCFDrr_nt || Opc == VE::BRCFDir_nt ||
90+
Opc == VE::BRCFDrr_t || Opc == VE::BRCFDir_t ||
91+
Opc == VE::BRCFSrr || Opc == VE::BRCFSir ||
92+
Opc == VE::BRCFSrr_nt || Opc == VE::BRCFSir_nt ||
93+
Opc == VE::BRCFSrr_t || Opc == VE::BRCFSir_t;
94+
}
95+
96+
static bool isIndirectBranchOpcode(int Opc) {
97+
return Opc == VE::BCFLari || Opc == VE::BCFLari ||
98+
Opc == VE::BCFLari_nt || Opc == VE::BCFLari_nt ||
99+
Opc == VE::BCFLari_t || Opc == VE::BCFLari_t ||
100+
Opc == VE::BCFLari || Opc == VE::BCFLari ||
101+
Opc == VE::BCFLari_nt || Opc == VE::BCFLari_nt ||
102+
Opc == VE::BCFLari_t || Opc == VE::BCFLari_t;
90103
}
91104

92105
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
@@ -165,14 +178,14 @@ bool VEInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
165178
return false;
166179
}
167180

168-
// TODO ...likewise if it ends with an indirect branch followed by an unconditional
181+
// ...likewise if it ends with an indirect branch followed by an unconditional
169182
// branch.
170-
// if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
171-
// I = LastInst;
172-
// if (AllowModify)
173-
// I->eraseFromParent();
174-
// return true;
175-
// }
183+
if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
184+
I = LastInst;
185+
if (AllowModify)
186+
I->eraseFromParent();
187+
return true;
188+
}
176189

177190
// Otherwise, can't handle this.
178191
return true;
@@ -190,13 +203,13 @@ unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB,
190203
if (Cond.empty()) {
191204
// Uncondition branch
192205
assert(!FBB && "Unconditional branch with multiple successors!");
193-
BuildMI(&MBB, DL, get(VE::BCRLa))
206+
BuildMI(&MBB, DL, get(VE::BRCFLa_t))
194207
.addMBB(TBB);
195208
return 1;
196209
}
197210

198211
// Conditional branch
199-
// (BCRir CC sy sz addr)
212+
// (BRCFir CC sy sz addr)
200213
assert(Cond[0].isImm() && Cond[2].isReg() && "not implemented");
201214

202215
unsigned opc[2];
@@ -206,19 +219,19 @@ unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB,
206219
unsigned Reg = Cond[2].getReg();
207220
if (IsIntegerCC(Cond[0].getImm())) {
208221
if (TRI->getRegSizeInBits(Reg, MRI) == 32) {
209-
opc[0] = VE::BCRWir;
210-
opc[1] = VE::BCRWrr;
222+
opc[0] = VE::BRCFWir;
223+
opc[1] = VE::BRCFWrr;
211224
} else {
212-
opc[0] = VE::BCRLir;
213-
opc[1] = VE::BCRLrr;
225+
opc[0] = VE::BRCFLir;
226+
opc[1] = VE::BRCFLrr;
214227
}
215228
} else {
216229
if (TRI->getRegSizeInBits(Reg, MRI) == 32) {
217-
opc[0] = VE::BCRSir;
218-
opc[1] = VE::BCRSrr;
230+
opc[0] = VE::BRCFSir;
231+
opc[1] = VE::BRCFSrr;
219232
} else {
220-
opc[0] = VE::BCRDir;
221-
opc[1] = VE::BCRDrr;
233+
opc[0] = VE::BRCFDir;
234+
opc[1] = VE::BRCFDrr;
222235
}
223236
}
224237
if (Cond[1].isImm()) {
@@ -238,7 +251,7 @@ unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB,
238251
if (!FBB)
239252
return 1;
240253

241-
BuildMI(&MBB, DL, get(VE::BCRLa))
254+
BuildMI(&MBB, DL, get(VE::BRCFLa_t))
242255
.addMBB(FBB);
243256
return 2;
244257
}
@@ -488,7 +501,7 @@ bool VEInstrInfo::expandExtendStackPseudo(MachineInstr &MI) const {
488501
// Next, add the true and fallthrough blocks as its successors.
489502
BB->addSuccessor(syscallMBB);
490503
BB->addSuccessor(sinkMBB);
491-
BuildMI(BB, dl, TII.get(VE::BCRLrr))
504+
BuildMI(BB, dl, TII.get(VE::BRCFLrr_t))
492505
.addImm(VECC::CC_IGE)
493506
.addReg(VE::SX11) // %sp
494507
.addReg(VE::SX8) // %sl

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