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atanasyantstellar
atanasyan
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tstellar
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Merging r374165:
------------------------------------------------------------------------ r374165 | atanasyan | 2019-10-09 06:12:27 -0700 (Wed, 09 Oct 2019) | 1 line [mips] Rename local variable. NFC ------------------------------------------------------------------------
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‎llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -3341,15 +3341,15 @@ bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc,
33413341

33423342
uint32_t ImmOp32 = covertDoubleImmToSingleImm(ImmOp64);
33433343

3344-
unsigned ATReg = getATReg(IDLoc);
3345-
if (!ATReg)
3344+
unsigned TmpReg = getATReg(IDLoc);
3345+
if (!TmpReg)
33463346
return true;
33473347

33483348
if (Lo_32(ImmOp64) == 0) {
3349-
if (loadImmediate(ImmOp32, ATReg, Mips::NoRegister, true, true, IDLoc, Out,
3349+
if (loadImmediate(ImmOp32, TmpReg, Mips::NoRegister, true, true, IDLoc, Out,
33503350
STI))
33513351
return true;
3352-
TOut.emitRR(Mips::MTC1, FirstReg, ATReg, IDLoc, STI);
3352+
TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI);
33533353
return false;
33543354
}
33553355

@@ -3372,7 +3372,7 @@ bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc,
33723372

33733373
if (emitPartialAddress(TOut, IDLoc, Sym))
33743374
return true;
3375-
TOut.emitRRX(Mips::LWC1, FirstReg, ATReg, MCOperand::createExpr(LoExpr),
3375+
TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr),
33763376
IDLoc, STI);
33773377
return false;
33783378
}
@@ -3393,8 +3393,8 @@ bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc,
33933393
uint32_t LoImmOp64 = Lo_32(ImmOp64);
33943394
uint32_t HiImmOp64 = Hi_32(ImmOp64);
33953395

3396-
unsigned ATReg = getATReg(IDLoc);
3397-
if (!ATReg)
3396+
unsigned TmpReg = getATReg(IDLoc);
3397+
if (!TmpReg)
33983398
return true;
33993399

34003400
if (LoImmOp64 == 0) {
@@ -3434,17 +3434,17 @@ bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc,
34343434
return true;
34353435

34363436
if (isABI_N64())
3437-
TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),
3437+
TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
34383438
IDLoc, STI);
34393439
else
3440-
TOut.emitRRX(Mips::ADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),
3440+
TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
34413441
IDLoc, STI);
34423442

34433443
if (isABI_N32() || isABI_N64())
3444-
TOut.emitRRI(Mips::LD, FirstReg, ATReg, 0, IDLoc, STI);
3444+
TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI);
34453445
else {
3446-
TOut.emitRRI(Mips::LW, FirstReg, ATReg, 0, IDLoc, STI);
3447-
TOut.emitRRI(Mips::LW, nextReg(FirstReg), ATReg, 4, IDLoc, STI);
3446+
TOut.emitRRI(Mips::LW, FirstReg, TmpReg, 0, IDLoc, STI);
3447+
TOut.emitRRI(Mips::LW, nextReg(FirstReg), TmpReg, 4, IDLoc, STI);
34483448
}
34493449
return false;
34503450
}
@@ -3465,24 +3465,24 @@ bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU,
34653465
uint32_t LoImmOp64 = Lo_32(ImmOp64);
34663466
uint32_t HiImmOp64 = Hi_32(ImmOp64);
34673467

3468-
unsigned ATReg = getATReg(IDLoc);
3469-
if (!ATReg)
3468+
unsigned TmpReg = getATReg(IDLoc);
3469+
if (!TmpReg)
34703470
return true;
34713471

34723472
if ((LoImmOp64 == 0) &&
34733473
!((HiImmOp64 & 0xffff0000) && (HiImmOp64 & 0x0000ffff))) {
34743474
// FIXME: In the case where the constant is zero, we can load the
34753475
// register directly from the zero register.
3476-
if (loadImmediate(HiImmOp64, ATReg, Mips::NoRegister, true, true, IDLoc,
3476+
if (loadImmediate(HiImmOp64, TmpReg, Mips::NoRegister, true, true, IDLoc,
34773477
Out, STI))
34783478
return true;
34793479
if (isABI_N32() || isABI_N64())
3480-
TOut.emitRR(Mips::DMTC1, FirstReg, ATReg, IDLoc, STI);
3480+
TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI);
34813481
else if (hasMips32r2()) {
34823482
TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
3483-
TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, ATReg, IDLoc, STI);
3483+
TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI);
34843484
} else {
3485-
TOut.emitRR(Mips::MTC1, nextReg(FirstReg), ATReg, IDLoc, STI);
3485+
TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI);
34863486
TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
34873487
}
34883488
return false;
@@ -3509,7 +3509,7 @@ bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU,
35093509
if (emitPartialAddress(TOut, IDLoc, Sym))
35103510
return true;
35113511

3512-
TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, ATReg,
3512+
TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, TmpReg,
35133513
MCOperand::createExpr(LoExpr), IDLoc, STI);
35143514

35153515
return false;

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