Merging r369093:

zmodem · zmodem · commit 74ed1f264156 · 2019-08-22T13:42:47.000Z
------------------------------------------------------------------------ r369093 | lewis-revill | 2019-08-16 12:23:56 +0200 (Fri, 16 Aug 2019) | 11 lines [RISCV] Add inline asm constraint A for RISC-V This allows the constraint A to be used in inline asm for RISC-V, which allows an address held in a register to be used. This patch adds the minimal amount of code required to get operands with the right constraints to compile. Differential Revision: https://reviews.llvm.org/D54295 ------------------------------------------------------------------------ llvm-svn: 369649
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
@@ -60,6 +60,10 @@ bool RISCVTargetInfo::validateAsmConstraint(
     // A floating-point register.
     Info.setAllowsRegister();
     return true;
+  case 'A':
+    // An address that is held in a general-purpose register.
+    Info.setAllowsMemory();
+    return true;
   }
 }
 
diff --git a/clang/test/CodeGen/riscv-inline-asm.c b/clang/test/CodeGen/riscv-inline-asm.c
@@ -38,3 +38,9 @@ void test_f() {
 // CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
   asm volatile ("" :: "f"(d));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}

Original file line number	Diff line number	Diff line change
`@@ -60,6 +60,10 @@ bool RISCVTargetInfo::validateAsmConstraint(`
`60`	`60`	`// A floating-point register.`
`61`	`61`	`Info.setAllowsRegister();`
`62`	`62`	`return true;`
	`63`	`+ case 'A':`
	`64`	`+ // An address that is held in a general-purpose register.`
	`65`	`+ Info.setAllowsMemory();`
	`66`	`+ return true;`
`63`	`67`	`}`
`64`	`68`	`}`
`65`	`69`