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[X86] Disable combineConcatVectors for vXi1 vectors.
I'm not convinced the code this calls is properly vetted for vXi1 vectors. Experimental vector widening legalization testing for D55251 is now hitting an assertion failure inside EltsFromConsecutiveLoads. This is occurring from a v2i1 load having a store size different than its VT size. Hopefully this commit will keep such issues from happening. llvm-svn: 366405
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‎llvm/lib/Target/X86/X86ISelLowering.cpp

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@@ -43730,6 +43730,10 @@ static SDValue combineConcatVectors(SDNode *N, SelectionDAG &DAG,
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EVT SrcVT = N->getOperand(0).getValueType();
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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// Don't do anything for i1 vectors.
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if (VT.getVectorElementType() == MVT::i1)
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return SDValue();
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if (Subtarget.hasAVX() && TLI.isTypeLegal(VT) && TLI.isTypeLegal(SrcVT)) {
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SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
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if (SDValue R = combineConcatVectorOps(SDLoc(N), VT.getSimpleVT(), Ops, DAG,

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