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Merging r367019:
------------------------------------------------------------------------ r367019 | chill | 2019-07-25 15:56:04 +0200 (Thu, 25 Jul 2019) | 10 lines [AArch64][SVE] Allow explicit size specifier for predicate operand ... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue supporting the exsting behaviour of not requiring an explicit size specifier. The preferred disasembly is *with* the specifier. This is implemented by redefining intruction forms to require vector predicates with explicit size and adding aliases, which allow a predicate with no size. Differential Revision: https://reviews.llvm.org/D65145 ------------------------------------------------------------------------ llvm-svn: 369086
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7 files changed

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‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 15 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -403,20 +403,20 @@ multiclass sve_int_count_r_x64<bits<5> opc, string asm> {
403403
}
404404

405405
class sve_int_count_v<bits<2> sz8_64, bits<5> opc, string asm,
406-
ZPRRegOp zprty>
407-
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, PPRAny:$Pg),
408-
asm, "\t$Zdn, $Pg",
406+
ZPRRegOp zprty, PPRRegOp pprty>
407+
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, pprty:$Pm),
408+
asm, "\t$Zdn, $Pm",
409409
"",
410410
[]>, Sched<[]> {
411-
bits<4> Pg;
411+
bits<4> Pm;
412412
bits<5> Zdn;
413413
let Inst{31-24} = 0b00100101;
414414
let Inst{23-22} = sz8_64;
415415
let Inst{21-19} = 0b101;
416416
let Inst{18-16} = opc{4-2};
417417
let Inst{15-11} = 0b10000;
418418
let Inst{10-9} = opc{1-0};
419-
let Inst{8-5} = Pg;
419+
let Inst{8-5} = Pm;
420420
let Inst{4-0} = Zdn;
421421

422422
let Constraints = "$Zdn = $_Zdn";
@@ -425,9 +425,16 @@ class sve_int_count_v<bits<2> sz8_64, bits<5> opc, string asm,
425425
}
426426

427427
multiclass sve_int_count_v<bits<5> opc, string asm> {
428-
def _H : sve_int_count_v<0b01, opc, asm, ZPR16>;
429-
def _S : sve_int_count_v<0b10, opc, asm, ZPR32>;
430-
def _D : sve_int_count_v<0b11, opc, asm, ZPR64>;
428+
def _H : sve_int_count_v<0b01, opc, asm, ZPR16, PPR16>;
429+
def _S : sve_int_count_v<0b10, opc, asm, ZPR32, PPR32>;
430+
def _D : sve_int_count_v<0b11, opc, asm, ZPR64, PPR64>;
431+
432+
def : InstAlias<asm # "\t$Zdn, $Pm",
433+
(!cast<Instruction>(NAME # "_H") ZPR16:$Zdn, PPRAny:$Pm), 0>;
434+
def : InstAlias<asm # "\t$Zdn, $Pm",
435+
(!cast<Instruction>(NAME # "_S") ZPR32:$Zdn, PPRAny:$Pm), 0>;
436+
def : InstAlias<asm # "\t$Zdn, $Pm",
437+
(!cast<Instruction>(NAME # "_D") ZPR64:$Zdn, PPRAny:$Pm), 0>;
431438
}
432439

433440
class sve_int_pcount_pred<bits<2> sz8_64, bits<4> opc, string asm,

‎llvm/test/MC/AArch64/SVE/decp.s

Lines changed: 22 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -56,19 +56,37 @@ decp xzr, p15.d
5656
// CHECK-UNKNOWN: ff 89 ed 25 <unknown>
5757

5858
decp z31.h, p15
59-
// CHECK-INST: decp z31.h, p15
59+
// CHECK-INST: decp z31.h, p15.h
60+
// CHECK-ENCODING: [0xff,0x81,0x6d,0x25]
61+
// CHECK-ERROR: instruction requires: sve
62+
// CHECK-UNKNOWN: ff 81 6d 25 <unknown>
63+
64+
decp z31.h, p15.h
65+
// CHECK-INST: decp z31.h, p15.h
6066
// CHECK-ENCODING: [0xff,0x81,0x6d,0x25]
6167
// CHECK-ERROR: instruction requires: sve
6268
// CHECK-UNKNOWN: ff 81 6d 25 <unknown>
6369

6470
decp z31.s, p15
65-
// CHECK-INST: decp z31.s, p15
71+
// CHECK-INST: decp z31.s, p15.s
72+
// CHECK-ENCODING: [0xff,0x81,0xad,0x25]
73+
// CHECK-ERROR: instruction requires: sve
74+
// CHECK-UNKNOWN: ff 81 ad 25 <unknown>
75+
76+
decp z31.s, p15.s
77+
// CHECK-INST: decp z31.s, p15.s
6678
// CHECK-ENCODING: [0xff,0x81,0xad,0x25]
6779
// CHECK-ERROR: instruction requires: sve
6880
// CHECK-UNKNOWN: ff 81 ad 25 <unknown>
6981

7082
decp z31.d, p15
71-
// CHECK-INST: decp z31.d, p15
83+
// CHECK-INST: decp z31.d, p15.d
84+
// CHECK-ENCODING: [0xff,0x81,0xed,0x25]
85+
// CHECK-ERROR: instruction requires: sve
86+
// CHECK-UNKNOWN: ff 81 ed 25 <unknown>
87+
88+
decp z31.d, p15.d
89+
// CHECK-INST: decp z31.d, p15.d
7290
// CHECK-ENCODING: [0xff,0x81,0xed,0x25]
7391
// CHECK-ERROR: instruction requires: sve
7492
// CHECK-UNKNOWN: ff 81 ed 25 <unknown>
@@ -83,7 +101,7 @@ movprfx z31, z6
83101
// CHECK-ERROR: instruction requires: sve
84102
// CHECK-UNKNOWN: df bc 20 04 <unknown>
85103

86-
decp z31.d, p15
104+
decp z31.d, p15.d
87105
// CHECK-INST: decp z31.d, p15
88106
// CHECK-ENCODING: [0xff,0x81,0xed,0x25]
89107
// CHECK-ERROR: instruction requires: sve

‎llvm/test/MC/AArch64/SVE/incp.s

Lines changed: 23 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -56,19 +56,37 @@ incp xzr, p15.d
5656
// CHECK-UNKNOWN: ff 89 ec 25 <unknown>
5757

5858
incp z31.h, p15
59-
// CHECK-INST: incp z31.h, p15
59+
// CHECK-INST: incp z31.h, p15.h
60+
// CHECK-ENCODING: [0xff,0x81,0x6c,0x25]
61+
// CHECK-ERROR: instruction requires: sve
62+
// CHECK-UNKNOWN: ff 81 6c 25 <unknown>
63+
64+
incp z31.h, p15.h
65+
// CHECK-INST: incp z31.h, p15.h
6066
// CHECK-ENCODING: [0xff,0x81,0x6c,0x25]
6167
// CHECK-ERROR: instruction requires: sve
6268
// CHECK-UNKNOWN: ff 81 6c 25 <unknown>
6369

6470
incp z31.s, p15
65-
// CHECK-INST: incp z31.s, p15
71+
// CHECK-INST: incp z31.s, p15.s
72+
// CHECK-ENCODING: [0xff,0x81,0xac,0x25]
73+
// CHECK-ERROR: instruction requires: sve
74+
// CHECK-UNKNOWN: ff 81 ac 25 <unknown>
75+
76+
incp z31.s, p15.s
77+
// CHECK-INST: incp z31.s, p15.s
6678
// CHECK-ENCODING: [0xff,0x81,0xac,0x25]
6779
// CHECK-ERROR: instruction requires: sve
6880
// CHECK-UNKNOWN: ff 81 ac 25 <unknown>
6981

7082
incp z31.d, p15
71-
// CHECK-INST: incp z31.d, p15
83+
// CHECK-INST: incp z31.d, p15.d
84+
// CHECK-ENCODING: [0xff,0x81,0xec,0x25]
85+
// CHECK-ERROR: instruction requires: sve
86+
// CHECK-UNKNOWN: ff 81 ec 25 <unknown>
87+
88+
incp z31.d, p15.d
89+
// CHECK-INST: incp z31.d, p15.d
7290
// CHECK-ENCODING: [0xff,0x81,0xec,0x25]
7391
// CHECK-ERROR: instruction requires: sve
7492
// CHECK-UNKNOWN: ff 81 ec 25 <unknown>
@@ -83,8 +101,8 @@ movprfx z31, z6
83101
// CHECK-ERROR: instruction requires: sve
84102
// CHECK-UNKNOWN: df bc 20 04 <unknown>
85103

86-
incp z31.d, p15
87-
// CHECK-INST: incp z31.d, p15
104+
incp z31.d, p15.d
105+
// CHECK-INST: incp z31.d, p15.d
88106
// CHECK-ENCODING: [0xff,0x81,0xec,0x25]
89107
// CHECK-ERROR: instruction requires: sve
90108
// CHECK-UNKNOWN: ff 81 ec 25 <unknown>

‎llvm/test/MC/AArch64/SVE/sqdecp.s

Lines changed: 23 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -56,19 +56,37 @@ sqdecp xzr, p15.d, wzr
5656
// CHECK-UNKNOWN: ff 89 ea 25 <unknown>
5757

5858
sqdecp z0.h, p0
59-
// CHECK-INST: sqdecp z0.h, p0
59+
// CHECK-INST: sqdecp z0.h, p0.h
60+
// CHECK-ENCODING: [0x00,0x80,0x6a,0x25]
61+
// CHECK-ERROR: instruction requires: sve
62+
// CHECK-UNKNOWN: 00 80 6a 25 <unknown>
63+
64+
sqdecp z0.h, p0.h
65+
// CHECK-INST: sqdecp z0.h, p0.h
6066
// CHECK-ENCODING: [0x00,0x80,0x6a,0x25]
6167
// CHECK-ERROR: instruction requires: sve
6268
// CHECK-UNKNOWN: 00 80 6a 25 <unknown>
6369

6470
sqdecp z0.s, p0
65-
// CHECK-INST: sqdecp z0.s, p0
71+
// CHECK-INST: sqdecp z0.s, p0.s
72+
// CHECK-ENCODING: [0x00,0x80,0xaa,0x25]
73+
// CHECK-ERROR: instruction requires: sve
74+
// CHECK-UNKNOWN: 00 80 aa 25 <unknown>
75+
76+
sqdecp z0.s, p0.s
77+
// CHECK-INST: sqdecp z0.s, p0.s
6678
// CHECK-ENCODING: [0x00,0x80,0xaa,0x25]
6779
// CHECK-ERROR: instruction requires: sve
6880
// CHECK-UNKNOWN: 00 80 aa 25 <unknown>
6981

7082
sqdecp z0.d, p0
71-
// CHECK-INST: sqdecp z0.d, p0
83+
// CHECK-INST: sqdecp z0.d, p0.d
84+
// CHECK-ENCODING: [0x00,0x80,0xea,0x25]
85+
// CHECK-ERROR: instruction requires: sve
86+
// CHECK-UNKNOWN: 00 80 ea 25 <unknown>
87+
88+
sqdecp z0.d, p0.d
89+
// CHECK-INST: sqdecp z0.d, p0.d
7290
// CHECK-ENCODING: [0x00,0x80,0xea,0x25]
7391
// CHECK-ERROR: instruction requires: sve
7492
// CHECK-UNKNOWN: 00 80 ea 25 <unknown>
@@ -83,8 +101,8 @@ movprfx z0, z7
83101
// CHECK-ERROR: instruction requires: sve
84102
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
85103

86-
sqdecp z0.d, p0
87-
// CHECK-INST: sqdecp z0.d, p0
104+
sqdecp z0.d, p0.d
105+
// CHECK-INST: sqdecp z0.d, p0.d
88106
// CHECK-ENCODING: [0x00,0x80,0xea,0x25]
89107
// CHECK-ERROR: instruction requires: sve
90108
// CHECK-UNKNOWN: 00 80 ea 25 <unknown>

‎llvm/test/MC/AArch64/SVE/sqincp.s

Lines changed: 23 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -56,19 +56,37 @@ sqincp xzr, p15.d, wzr
5656
// CHECK-UNKNOWN: ff 89 e8 25 <unknown>
5757

5858
sqincp z0.h, p0
59-
// CHECK-INST: sqincp z0.h, p0
59+
// CHECK-INST: sqincp z0.h, p0.h
60+
// CHECK-ENCODING: [0x00,0x80,0x68,0x25]
61+
// CHECK-ERROR: instruction requires: sve
62+
// CHECK-UNKNOWN: 00 80 68 25 <unknown>
63+
64+
sqincp z0.h, p0.h
65+
// CHECK-INST: sqincp z0.h, p0.h
6066
// CHECK-ENCODING: [0x00,0x80,0x68,0x25]
6167
// CHECK-ERROR: instruction requires: sve
6268
// CHECK-UNKNOWN: 00 80 68 25 <unknown>
6369

6470
sqincp z0.s, p0
65-
// CHECK-INST: sqincp z0.s, p0
71+
// CHECK-INST: sqincp z0.s, p0.s
72+
// CHECK-ENCODING: [0x00,0x80,0xa8,0x25]
73+
// CHECK-ERROR: instruction requires: sve
74+
// CHECK-UNKNOWN: 00 80 a8 25 <unknown>
75+
76+
sqincp z0.s, p0.s
77+
// CHECK-INST: sqincp z0.s, p0.s
6678
// CHECK-ENCODING: [0x00,0x80,0xa8,0x25]
6779
// CHECK-ERROR: instruction requires: sve
6880
// CHECK-UNKNOWN: 00 80 a8 25 <unknown>
6981

7082
sqincp z0.d, p0
71-
// CHECK-INST: sqincp z0.d, p0
83+
// CHECK-INST: sqincp z0.d, p0.d
84+
// CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
85+
// CHECK-ERROR: instruction requires: sve
86+
// CHECK-UNKNOWN: 00 80 e8 25 <unknown>
87+
88+
sqincp z0.d, p0.d
89+
// CHECK-INST: sqincp z0.d, p0.d
7290
// CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
7391
// CHECK-ERROR: instruction requires: sve
7492
// CHECK-UNKNOWN: 00 80 e8 25 <unknown>
@@ -83,8 +101,8 @@ movprfx z0, z7
83101
// CHECK-ERROR: instruction requires: sve
84102
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
85103

86-
sqincp z0.d, p0
87-
// CHECK-INST: sqincp z0.d, p0
104+
sqincp z0.d, p0.d
105+
// CHECK-INST: sqincp z0.d, p0.d
88106
// CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
89107
// CHECK-ERROR: instruction requires: sve
90108
// CHECK-UNKNOWN: 00 80 e8 25 <unknown>

‎llvm/test/MC/AArch64/SVE/uqdecp.s

Lines changed: 23 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -56,19 +56,37 @@ uqdecp wzr, p15.d
5656
// CHECK-UNKNOWN: ff 89 eb 25 <unknown>
5757

5858
uqdecp z0.h, p0
59-
// CHECK-INST: uqdecp z0.h, p0
59+
// CHECK-INST: uqdecp z0.h, p0.h
60+
// CHECK-ENCODING: [0x00,0x80,0x6b,0x25]
61+
// CHECK-ERROR: instruction requires: sve
62+
// CHECK-UNKNOWN: 00 80 6b 25 <unknown>
63+
64+
uqdecp z0.h, p0.h
65+
// CHECK-INST: uqdecp z0.h, p0.h
6066
// CHECK-ENCODING: [0x00,0x80,0x6b,0x25]
6167
// CHECK-ERROR: instruction requires: sve
6268
// CHECK-UNKNOWN: 00 80 6b 25 <unknown>
6369

6470
uqdecp z0.s, p0
65-
// CHECK-INST: uqdecp z0.s, p0
71+
// CHECK-INST: uqdecp z0.s, p0.s
72+
// CHECK-ENCODING: [0x00,0x80,0xab,0x25]
73+
// CHECK-ERROR: instruction requires: sve
74+
// CHECK-UNKNOWN: 00 80 ab 25 <unknown>
75+
76+
uqdecp z0.s, p0.s
77+
// CHECK-INST: uqdecp z0.s, p0.s
6678
// CHECK-ENCODING: [0x00,0x80,0xab,0x25]
6779
// CHECK-ERROR: instruction requires: sve
6880
// CHECK-UNKNOWN: 00 80 ab 25 <unknown>
6981

7082
uqdecp z0.d, p0
71-
// CHECK-INST: uqdecp z0.d, p0
83+
// CHECK-INST: uqdecp z0.d, p0.d
84+
// CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
85+
// CHECK-ERROR: instruction requires: sve
86+
// CHECK-UNKNOWN: 00 80 eb 25 <unknown>
87+
88+
uqdecp z0.d, p0.d
89+
// CHECK-INST: uqdecp z0.d, p0.d
7290
// CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
7391
// CHECK-ERROR: instruction requires: sve
7492
// CHECK-UNKNOWN: 00 80 eb 25 <unknown>
@@ -83,8 +101,8 @@ movprfx z0, z7
83101
// CHECK-ERROR: instruction requires: sve
84102
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
85103

86-
uqdecp z0.d, p0
87-
// CHECK-INST: uqdecp z0.d, p0
104+
uqdecp z0.d, p0.d
105+
// CHECK-INST: uqdecp z0.d, p0.d
88106
// CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
89107
// CHECK-ERROR: instruction requires: sve
90108
// CHECK-UNKNOWN: 00 80 eb 25 <unknown>

‎llvm/test/MC/AArch64/SVE/uqincp.s

Lines changed: 23 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -56,19 +56,37 @@ uqincp wzr, p15.d
5656
// CHECK-UNKNOWN: ff 89 e9 25 <unknown>
5757

5858
uqincp z0.h, p0
59-
// CHECK-INST: uqincp z0.h, p0
59+
// CHECK-INST: uqincp z0.h, p0.h
60+
// CHECK-ENCODING: [0x00,0x80,0x69,0x25]
61+
// CHECK-ERROR: instruction requires: sve
62+
// CHECK-UNKNOWN: 00 80 69 25 <unknown>
63+
64+
uqincp z0.h, p0.h
65+
// CHECK-INST: uqincp z0.h, p0.h
6066
// CHECK-ENCODING: [0x00,0x80,0x69,0x25]
6167
// CHECK-ERROR: instruction requires: sve
6268
// CHECK-UNKNOWN: 00 80 69 25 <unknown>
6369

6470
uqincp z0.s, p0
65-
// CHECK-INST: uqincp z0.s, p0
71+
// CHECK-INST: uqincp z0.s, p0.s
72+
// CHECK-ENCODING: [0x00,0x80,0xa9,0x25]
73+
// CHECK-ERROR: instruction requires: sve
74+
// CHECK-UNKNOWN: 00 80 a9 25 <unknown>
75+
76+
uqincp z0.s, p0.s
77+
// CHECK-INST: uqincp z0.s, p0.s
6678
// CHECK-ENCODING: [0x00,0x80,0xa9,0x25]
6779
// CHECK-ERROR: instruction requires: sve
6880
// CHECK-UNKNOWN: 00 80 a9 25 <unknown>
6981

7082
uqincp z0.d, p0
71-
// CHECK-INST: uqincp z0.d, p0
83+
// CHECK-INST: uqincp z0.d, p0.d
84+
// CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
85+
// CHECK-ERROR: instruction requires: sve
86+
// CHECK-UNKNOWN: 00 80 e9 25 <unknown>
87+
88+
uqincp z0.d, p0.d
89+
// CHECK-INST: uqincp z0.d, p0.d
7290
// CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
7391
// CHECK-ERROR: instruction requires: sve
7492
// CHECK-UNKNOWN: 00 80 e9 25 <unknown>
@@ -83,8 +101,8 @@ movprfx z0, z7
83101
// CHECK-ERROR: instruction requires: sve
84102
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
85103

86-
uqincp z0.d, p0
87-
// CHECK-INST: uqincp z0.d, p0
104+
uqincp z0.d, p0.d
105+
// CHECK-INST: uqincp z0.d, p0.d
88106
// CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
89107
// CHECK-ERROR: instruction requires: sve
90108
// CHECK-UNKNOWN: 00 80 e9 25 <unknown>

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