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[MachineVerifier] retrofit iterators with range for. NFC
Summary: Reviewing failures identified in D78586, I was finding the identifiers for these iterators hard to read. Reviewers: efriedma, MaskRay, jyknight Reviewed By: MaskRay Subscribers: hiraditya, llvm-commits, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D78849
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‎llvm/lib/CodeGen/MachineVerifier.cpp

Lines changed: 73 additions & 98 deletions
Original file line numberDiff line numberDiff line change
@@ -168,20 +168,14 @@ namespace {
168168

169169
// Same for a full set.
170170
bool addRequired(const RegSet &RS) {
171-
bool changed = false;
172-
for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
173-
if (addRequired(*I))
174-
changed = true;
175-
return changed;
171+
return llvm::any_of(RS,
172+
[this](unsigned Reg) { return addRequired(Reg); });
176173
}
177174

178175
// Same for a full map.
179176
bool addRequired(const RegMap &RM) {
180-
bool changed = false;
181-
for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
182-
if (addRequired(I->first))
183-
changed = true;
184-
return changed;
177+
return llvm::any_of(
178+
RM, [this](const auto &P) { return addRequired(P.first); });
185179
}
186180

187181
// Live-out registers are either in regsLiveOut or vregsPassed.
@@ -379,43 +373,40 @@ unsigned MachineVerifier::verify(MachineFunction &MF) {
379373
verifyProperties(MF);
380374

381375
visitMachineFunctionBefore();
382-
for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
383-
MFI!=MFE; ++MFI) {
384-
visitMachineBasicBlockBefore(&*MFI);
376+
for (const MachineBasicBlock &MBB : MF) {
377+
visitMachineBasicBlockBefore(&MBB);
385378
// Keep track of the current bundle header.
386379
const MachineInstr *CurBundle = nullptr;
387380
// Do we expect the next instruction to be part of the same bundle?
388381
bool InBundle = false;
389382

390-
for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
391-
MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
392-
if (MBBI->getParent() != &*MFI) {
393-
report("Bad instruction parent pointer", &*MFI);
394-
errs() << "Instruction: " << *MBBI;
383+
for (const MachineInstr &MI : MBB.instrs()) {
384+
if (MI.getParent() != &MBB) {
385+
report("Bad instruction parent pointer", &MBB);
386+
errs() << "Instruction: " << MI;
395387
continue;
396388
}
397389

398390
// Check for consistent bundle flags.
399-
if (InBundle && !MBBI->isBundledWithPred())
391+
if (InBundle && !MI.isBundledWithPred())
400392
report("Missing BundledPred flag, "
401393
"BundledSucc was set on predecessor",
402-
&*MBBI);
403-
if (!InBundle && MBBI->isBundledWithPred())
394+
&MI);
395+
if (!InBundle && MI.isBundledWithPred())
404396
report("BundledPred flag is set, "
405397
"but BundledSucc not set on predecessor",
406-
&*MBBI);
398+
&MI);
407399

408400
// Is this a bundle header?
409-
if (!MBBI->isInsideBundle()) {
401+
if (!MI.isInsideBundle()) {
410402
if (CurBundle)
411403
visitMachineBundleAfter(CurBundle);
412-
CurBundle = &*MBBI;
404+
CurBundle = &MI;
413405
visitMachineBundleBefore(CurBundle);
414406
} else if (!CurBundle)
415-
report("No bundle header", &*MBBI);
416-
visitMachineInstrBefore(&*MBBI);
417-
for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
418-
const MachineInstr &MI = *MBBI;
407+
report("No bundle header", &MI);
408+
visitMachineInstrBefore(&MI);
409+
for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
419410
const MachineOperand &Op = MI.getOperand(I);
420411
if (Op.getParent() != &MI) {
421412
// Make sure to use correct addOperand / RemoveOperand / ChangeTo
@@ -426,16 +417,16 @@ unsigned MachineVerifier::verify(MachineFunction &MF) {
426417
visitMachineOperand(&Op, I);
427418
}
428419

429-
visitMachineInstrAfter(&*MBBI);
420+
visitMachineInstrAfter(&MI);
430421

431422
// Was this the last bundled instruction?
432-
InBundle = MBBI->isBundledWithSucc();
423+
InBundle = MI.isBundledWithSucc();
433424
}
434425
if (CurBundle)
435426
visitMachineBundleAfter(CurBundle);
436427
if (InBundle)
437-
report("BundledSucc flag set on last instruction in block", &MFI->back());
438-
visitMachineBasicBlockAfter(&*MFI);
428+
report("BundledSucc flag set on last instruction in block", &MBB.back());
429+
visitMachineBasicBlockAfter(&MBB);
439430
}
440431
visitMachineFunctionAfter();
441432

@@ -546,9 +537,8 @@ void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
546537
BBInfo &MInfo = MBBInfoMap[MBB];
547538
if (!MInfo.reachable) {
548539
MInfo.reachable = true;
549-
for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
550-
SuE = MBB->succ_end(); SuI != SuE; ++SuI)
551-
markReachable(*SuI);
540+
for (const MachineBasicBlock *Succ : MBB->successors())
541+
markReachable(Succ);
552542
}
553543
}
554544

@@ -640,14 +630,13 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
640630
}
641631

642632
// Check the predecessor list.
643-
for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
644-
E = MBB->pred_end(); I != E; ++I) {
645-
if (!FunctionBlocks.count(*I))
633+
for (const MachineBasicBlock *Pred : MBB->predecessors()) {
634+
if (!FunctionBlocks.count(Pred))
646635
report("MBB has predecessor that isn't part of the function.", MBB);
647-
if (!MBBInfoMap[*I].Succs.count(MBB)) {
636+
if (!MBBInfoMap[Pred].Succs.count(MBB)) {
648637
report("Inconsistent CFG", MBB);
649638
errs() << "MBB is not in the successor list of the predecessor "
650-
<< printMBBReference(*(*I)) << ".\n";
639+
<< printMBBReference(*Pred) << ".\n";
651640
}
652641
}
653642

@@ -670,8 +659,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
670659
// check whether its answers match up with reality.
671660
if (!TBB && !FBB) {
672661
// Block falls through to its successor.
673-
MachineFunction::const_iterator MBBI = MBB->getIterator();
674-
++MBBI;
662+
MachineFunction::const_iterator MBBI = std::next(MBB->getIterator());
675663
if (MBBI == MF->end()) {
676664
// It's possible that the block legitimately ends with a noreturn
677665
// call or an unreachable, in which case it won't actually fall
@@ -728,8 +716,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
728716
}
729717
} else if (TBB && !FBB && !Cond.empty()) {
730718
// Block conditionally branches somewhere, otherwise falls through.
731-
MachineFunction::const_iterator MBBI = MBB->getIterator();
732-
++MBBI;
719+
MachineFunction::const_iterator MBBI = std::next(MBB->getIterator());
733720
if (MBBI == MF->end()) {
734721
report("MBB conditionally falls through out of function!", MBB);
735722
} else if (MBB->succ_size() == 1) {
@@ -1485,12 +1472,10 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
14851472
verifyInlineAsm(MI);
14861473

14871474
// Check the MachineMemOperands for basic consistency.
1488-
for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
1489-
E = MI->memoperands_end();
1490-
I != E; ++I) {
1491-
if ((*I)->isLoad() && !MI->mayLoad())
1475+
for (MachineMemOperand *Op : MI->memoperands()) {
1476+
if (Op->isLoad() && !MI->mayLoad())
14921477
report("Missing mayLoad flag", MI);
1493-
if ((*I)->isStore() && !MI->mayStore())
1478+
if (Op->isStore() && !MI->mayStore())
14941479
report("Missing mayStore flag", MI);
14951480
}
14961481

@@ -2101,10 +2086,10 @@ void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
21012086
// Kill any masked registers.
21022087
while (!regMasks.empty()) {
21032088
const uint32_t *Mask = regMasks.pop_back_val();
2104-
for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
2105-
if (Register::isPhysicalRegister(*I) &&
2106-
MachineOperand::clobbersPhysReg(Mask, *I))
2107-
regsDead.push_back(*I);
2089+
for (unsigned Reg : regsLive)
2090+
if (Register::isPhysicalRegister(Reg) &&
2091+
MachineOperand::clobbersPhysReg(Mask, Reg))
2092+
regsDead.push_back(Reg);
21082093
}
21092094
set_subtract(regsLive, regsDead); regsDead.clear();
21102095
set_union(regsLive, regsDefined); regsDefined.clear();
@@ -2301,11 +2286,10 @@ void MachineVerifier::calcRegsRequired() {
23012286
SmallPtrSet<const MachineBasicBlock*, 8> todo;
23022287
for (const auto &MBB : *MF) {
23032288
BBInfo &MInfo = MBBInfoMap[&MBB];
2304-
for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
2305-
PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
2306-
BBInfo &PInfo = MBBInfoMap[*PrI];
2289+
for (const MachineBasicBlock *Pred : MBB.predecessors()) {
2290+
BBInfo &PInfo = MBBInfoMap[Pred];
23072291
if (PInfo.addRequired(MInfo.vregsLiveIn))
2308-
todo.insert(*PrI);
2292+
todo.insert(Pred);
23092293
}
23102294
}
23112295

@@ -2315,13 +2299,12 @@ void MachineVerifier::calcRegsRequired() {
23152299
const MachineBasicBlock *MBB = *todo.begin();
23162300
todo.erase(MBB);
23172301
BBInfo &MInfo = MBBInfoMap[MBB];
2318-
for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
2319-
PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
2320-
if (*PrI == MBB)
2302+
for (const MachineBasicBlock *Pred : MBB->predecessors()) {
2303+
if (Pred == MBB)
23212304
continue;
2322-
BBInfo &SInfo = MBBInfoMap[*PrI];
2305+
BBInfo &SInfo = MBBInfoMap[Pred];
23232306
if (SInfo.addRequired(MInfo.vregsRequired))
2324-
todo.insert(*PrI);
2307+
todo.insert(Pred);
23252308
}
23262309
}
23272310
}
@@ -2405,23 +2388,19 @@ void MachineVerifier::visitMachineFunctionAfter() {
24052388
// Check for killed virtual registers that should be live out.
24062389
for (const auto &MBB : *MF) {
24072390
BBInfo &MInfo = MBBInfoMap[&MBB];
2408-
for (RegSet::iterator
2409-
I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
2410-
++I)
2411-
if (MInfo.regsKilled.count(*I)) {
2391+
for (unsigned VReg : MInfo.vregsRequired)
2392+
if (MInfo.regsKilled.count(VReg)) {
24122393
report("Virtual register killed in block, but needed live out.", &MBB);
2413-
errs() << "Virtual register " << printReg(*I)
2394+
errs() << "Virtual register " << printReg(VReg)
24142395
<< " is used after the block.\n";
24152396
}
24162397
}
24172398

24182399
if (!MF->empty()) {
24192400
BBInfo &MInfo = MBBInfoMap[&MF->front()];
2420-
for (RegSet::iterator
2421-
I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
2422-
++I) {
2401+
for (unsigned VReg : MInfo.vregsRequired) {
24232402
report("Virtual register defs don't dominate all uses.", MF);
2424-
report_context_vreg(*I);
2403+
report_context_vreg(VReg);
24252404
}
24262405
}
24272406

@@ -2783,19 +2762,18 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
27832762
VNI->def == LiveInts->getMBBStartIdx(&*MFI);
27842763

27852764
// Check that VNI is live-out of all predecessors.
2786-
for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
2787-
PE = MFI->pred_end(); PI != PE; ++PI) {
2788-
SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
2765+
for (const MachineBasicBlock *Pred : MFI->predecessors()) {
2766+
SlotIndex PEnd = LiveInts->getMBBEndIdx(Pred);
27892767
const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
27902768

27912769
// All predecessors must have a live-out value. However for a phi
27922770
// instruction with subregister intervals
27932771
// only one of the subregisters (not necessarily the current one) needs to
27942772
// be defined.
27952773
if (!PVNI && (LaneMask.none() || !IsPHI)) {
2796-
if (LiveRangeCalc::isJointlyDominated(*PI, Undefs, *Indexes))
2774+
if (LiveRangeCalc::isJointlyDominated(Pred, Undefs, *Indexes))
27972775
continue;
2798-
report("Register not marked live out of predecessor", *PI);
2776+
report("Register not marked live out of predecessor", Pred);
27992777
report_context(LR, Reg, LaneMask);
28002778
report_context(*VNI);
28012779
errs() << " live into " << printMBBReference(*MFI) << '@'
@@ -2806,10 +2784,10 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
28062784

28072785
// Only PHI-defs can take different predecessor values.
28082786
if (!IsPHI && PVNI != VNI) {
2809-
report("Different value live out of predecessor", *PI);
2787+
report("Different value live out of predecessor", Pred);
28102788
report_context(LR, Reg, LaneMask);
28112789
errs() << "Valno #" << PVNI->id << " live out of "
2812-
<< printMBBReference(*(*PI)) << '@' << PEnd << "\nValno #"
2790+
<< printMBBReference(*Pred) << '@' << PEnd << "\nValno #"
28132791
<< VNI->id << " live into " << printMBBReference(*MFI) << '@'
28142792
<< LiveInts->getMBBStartIdx(&*MFI) << '\n';
28152793
}
@@ -2865,10 +2843,9 @@ void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
28652843
report_context(LI);
28662844
for (unsigned comp = 0; comp != NumComp; ++comp) {
28672845
errs() << comp << ": valnos";
2868-
for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
2869-
E = LI.vni_end(); I!=E; ++I)
2870-
if (comp == ConEQ.getEqClass(*I))
2871-
errs() << ' ' << (*I)->id;
2846+
for (const VNInfo *I : LI.valnos)
2847+
if (comp == ConEQ.getEqClass(I))
2848+
errs() << ' ' << I->id;
28722849
errs() << '\n';
28732850
}
28742851
}
@@ -2955,31 +2932,29 @@ void MachineVerifier::verifyStackFrame() {
29552932

29562933
// Make sure the exit state of any predecessor is consistent with the entry
29572934
// state.
2958-
for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
2959-
E = MBB->pred_end(); I != E; ++I) {
2960-
if (Reachable.count(*I) &&
2961-
(SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
2962-
SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
2935+
for (const MachineBasicBlock *Pred : MBB->predecessors()) {
2936+
if (Reachable.count(Pred) &&
2937+
(SPState[Pred->getNumber()].ExitValue != BBState.EntryValue ||
2938+
SPState[Pred->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
29632939
report("The exit stack state of a predecessor is inconsistent.", MBB);
2964-
errs() << "Predecessor " << printMBBReference(*(*I))
2965-
<< " has exit state (" << SPState[(*I)->getNumber()].ExitValue
2966-
<< ", " << SPState[(*I)->getNumber()].ExitIsSetup << "), while "
2940+
errs() << "Predecessor " << printMBBReference(*Pred)
2941+
<< " has exit state (" << SPState[Pred->getNumber()].ExitValue
2942+
<< ", " << SPState[Pred->getNumber()].ExitIsSetup << "), while "
29672943
<< printMBBReference(*MBB) << " has entry state ("
29682944
<< BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
29692945
}
29702946
}
29712947

29722948
// Make sure the entry state of any successor is consistent with the exit
29732949
// state.
2974-
for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
2975-
E = MBB->succ_end(); I != E; ++I) {
2976-
if (Reachable.count(*I) &&
2977-
(SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
2978-
SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
2950+
for (const MachineBasicBlock *Succ : MBB->successors()) {
2951+
if (Reachable.count(Succ) &&
2952+
(SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
2953+
SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
29792954
report("The entry stack state of a successor is inconsistent.", MBB);
2980-
errs() << "Successor " << printMBBReference(*(*I))
2981-
<< " has entry state (" << SPState[(*I)->getNumber()].EntryValue
2982-
<< ", " << SPState[(*I)->getNumber()].EntryIsSetup << "), while "
2955+
errs() << "Successor " << printMBBReference(*Succ)
2956+
<< " has entry state (" << SPState[Succ->getNumber()].EntryValue
2957+
<< ", " << SPState[Succ->getNumber()].EntryIsSetup << "), while "
29832958
<< printMBBReference(*MBB) << " has exit state ("
29842959
<< BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
29852960
}

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