Search for Verification IP

WDT Verification IP

• The Watchdog Timer (WDT) regains control in case of system failure to increase application reliability.
• The WDT can generate a reset or an interrupt when the counter reaches a given timeout value.

GPIO Verification IP

• Available in native System Verilog (UVM/OVM/ VMM) and Verilog
• Unique development methodology to ensure the highest levels of quality

Simulation VIP for AMBA LTI

• LTI active and passive VIP supports both the specification version LTI-A and LTI-B

Simulation VIP for UCIE

• Support testbench language interfaces for SystemVerilog, UVM
• UVM building blocks

Universal Chiplet Interconnect Express (UCIe) Verification IP

• Supports Universal Chiplet Interconnect Express Specification Version 1.0, February 2022.

SPMI Verification IP

• Compliant with MIPI SPMI(1.0 and 2.0) specification.
• Supports multi-master and multi-slave model.

BoW Verification IP

• Compliant to ODSA Transaction and Link Layer Specification for BoW Interfaces and Bunch of Wires (BoW) PHY specification

USB4 v2.0 Verification IP

• Fully compliant with USB4 specification v2.0 (October 2022) and Connection Manager version 2.0.
• Supports USB3.2 Specification, Revision 1.1 and backward compatibility to USB2.0.

MASS Solution Verification IP

• Support full functionality of APHY as a physical layer
• Support Different PAL for multiple adaption layers for A-pkt conversion

UCIe Verification IP

• Available in native SystemVerilog (UVM/OVM /VMM) and Verilog
• Unique development methodology to ensure highest levels of quality

TCP/TCPSW Verification IP

• Available in native System Verilog (UVM/OVM/ VMM) and Verilog
• Unique development methodology to ensure the highest levels of quality

Simulation VIP for MIPI SoundWire-I3S

• Support testbench language interfaces for SystemVerilog and UVM
• Generates constrained-random bus traffic with predefined error injection

GPIO Verification IP

• Available in native System Verilog (UVM/OVM/ VMM) and Verilog
• Unique development methodology to ensure the highest levels of quality

HBM Verification IP

• Compliant to JEDEC HBM SDRAM Specification version JESD235.
• Supports connection to any HBM Memory Controller IP communicating with a JESD235 compliant HBM Memory Model.

AMBA 2.0 AHB Verification IP

AMBA APB Verification IP

MIPI CSI-2 with C phy Verification IP

• Compliant to MIPI CSI-2 Interface Specification version 1.1 and MIPI D-PHY version 1.1

AMBA 3 APB Verification IP

10G ETHERNET Verification IP

CJTAG (IEEE 1149.7) Verification IP

MIPI UniPro Verification IP

• Fully compliant with UniPro specification 1.41.00
• Supports TC0 and TC1 Traffic Classes
• Supports maximum of 4 lanes in each direction

Simulation VIP for AMBA APB

Simulation VIP for AMBA AXI

UART Verification IP