Papers by Antonio Ferrari
Universidade de Aveiro eBooks, Dec 1, 1999
The specification of a Virtual Campus System: a Design centered on the Learning Activity ________... more The specification of a Virtual Campus System: a Design centered on the Learning Activity _________________________________________________________________ 2.3.2. The architecture and implementation of our VCS _________________________ 2.4. SOME ISSUES DERIVED FROM THE DESIGN AND EXPERIMENTATION OF THE VIRTUAL CAMPUS____________________________________________________________________ 2.4.1. The user's interface issues____________________________________________ The learning organization issues _____________________________________________ 2.5. CONCLUSION: TOWARDS A SHIFT OF PARADIGM IN THE DESIGN OF THE NEXT GENERATION OF VIRTUAL CAMPUS__________________________________________________________ 3. RCTS: THE PORTUGUESE NETWORK FOR EDUCATION, SCIENCE AND TECHNOLOGY INVITED PAPER _____________________________________________ PEDRO VEIGA 11.4.2. (2) Aims of the evaluation ___________________________________________ 11.4.3. (3) Contributions of the evaluation to the development of the product ________ 11.4.4. (4) Contributions of the evaluation to the working process of the programme __ 12. MODELING A WEB-BASED EDUCATIONAL ENVIRONMENT ____________ ANA LUÍSA NEVES ET AL 12.1. INTRODUCTION _____________________________________________________ 12.2. ACTIVITIES, LEARNING PHILOSOPHIES AND COMPETENCIES___________________ 12.3. THE INTRANET______________________________________________________ 12.4. CONCLUSION _______________________________________________________ 13. HOW TO USE INTERACTIVITY IN AN EFFECTIVE WAY: A PROPOSAL __ CARLOS MANUEL SANTOS ET AL 13.1. INTRODUCTION _____________________________________________________ 13.2. PROBLEM SOLVING ORIENTED TUTORIAL_________________________________ 13.3. THEME PRESENTATION _______________________________________________ 13.3.1. Case study discussion ______________________________________________ 13.3.2. Introduction of new concepts ________________________________________ 13.3.3. Systemisation_____________________________________________________ 13.3.4. Working examples_________________________________________________ 13.3.5. Auto-assessment __________________________________________________ 13.4. CONCLUSION _______________________________________________________ 14. SIMULATIONS FOR FACILITATING SELF-TRAINING IN FLOW CYTOMETRY-DISCUSSION OF THE CONCEPT AND ITS UTILITY __________________________ FILIPE SANSONETTY ET AL 15. VIRTUAL REALITY IN SCIENCE EDUCATION: THE VIRTUAL WATER PROJECT __________________________________________________________________ JORGE FONSECA TRINDADE ET AL 15.1. INTRODUCTION _____________________________________________________ 15.2. GENERAL FEATURES OF THE PROJECT____________________________________ 15.3. CONCLUSION _______________________________________________________ 15.4. ACKNOWLEDGEMENTS _______________________________________________ 16. PLATINUM A FRAMEWORK FOR I*NET-BASED LEARNING AND TRAINING INVITED PAPER ____________________________________________________________ CHRISTOPH HORNUNG 16.1. INTRODUCTION _____________________________________________________ 16.2. CONCEPTS OF INTERNET-BASED LEARNING AND TRAINING____________________ 16.2.1. Introduction______________________________________________________ 16.2.2. Roles involved:
Page 1. Extensible multiplier-accumulator blocks for FPGAs António B. Ferrari(1), Rui R. Almeida(... more Page 1. Extensible multiplier-accumulator blocks for FPGAs António B. Ferrari(1), Rui R. Almeida(2), Rui E. Martins(1) ferrari@det.ua.pt, Rui.Almeida-Ext_NBS@ siemens.com, rmm@det.ua.pt (1) Department of Electronics and ...
Microprocessors and Microsystems, Jul 1, 2021
Abstract In this article the complexity and runtime performance of two Multiuser Detectors for Di... more Abstract In this article the complexity and runtime performance of two Multiuser Detectors for Direct Sequence-Code Division Multiple Access were evaluated in two different hardware platforms. The innovation and aim is to take advantage of present parallel hardware to bring Multiuser technology to present and future Base Stations in order to increase the capacity of the overall system, to reduce the transmission power by the mobile stations and to reduce base station hardware requirements, in Universal Mobile Telecommunications System. The detectors are based on the Frequency Shift Canceller concatenated with a Parallel Interference Canceller. This detector implies the inversion of multiple identical size small matrices and because of that it is very scalable contrary to other solutions/detectors that only permits a sequential implementation despite their lower complexity. Implementations for the Time Division-Code Division Multiple Access, in two software platforms one in OpenMP and the other in CUDA were done taking into account the carrier and doppler frequency offsets (offset different for each user). The result shows that this deployment aware real-time implementation of the Multiuser Detectors is possible with a Graphics Processor Unit being three times faster than required.
The paper analyses different techniques that might be employed in order to solve various problems... more The paper analyses different techniques that might be employed in order to solve various problems of combinatorial optimization and argues that the best results can be achieved by the use of software running on a general-purpose computer together with an FPGA-based reconfigurable co-processor. It suggests an architecture for a combinatorial coprocessor that is based on hardware templates and consists of reconfigurable functional and control units. Finally the paper demonstrates how the co-processor can be applied to two practical applications formulated over discrete matrices, the Boolean satisfiability and covering problems.
Microprocessors and Microsystems, Jul 1, 1991
Journal of Systems Architecture, Sep 1, 2003
Computer architecture has of late become a much more open area of research, with new RISC-type pr... more Computer architecture has of late become a much more open area of research, with new RISC-type processors enjoying significant commercial success. The author argues that such changes should be reflected in the curriculum, leading to a much closer interaction of computer architecture with VLSI design. After examining well-established curriculum guidelines, such as those proposed by the IEEE and ACM, a new computer architecture curriculum is proposed.<<ETX>>
Electrónica e Telecomunicações, 2002
Resumo-Neste artigo considera-se em detalhe o problema de satisfação booleana (SAT) e descrevem-s... more Resumo-Neste artigo considera-se em detalhe o problema de satisfação booleana (SAT) e descrevem-se os algoritmos discretos completos que são normalmente utilizados para a sua solução. É mostrado que SAT tem inúmeras aplicações práticas. Portanto, o desenvolvimento e a implementação de algoritmos eficientes assumem actualmente grande importância. Finalmente, são analizadas várias realizações de algoritmos baseadas em hardware reconfigurável e é comparado o seu desempenho.
Design, Automation, and Test in Europe, Mar 4, 2002
The Kluwer international series in engineering and computer science, 2003
Complex combinatorial problems appear in various systems providing real time processing. The majo... more Complex combinatorial problems appear in various systems providing real time processing. The majority of combinatorial problems that have to be solved are NP-complete and it limits the use of the respective mathematical models, methods and algorithms for a number of practical applications, for instance, for reactive embedded systems. The paper suggests architecture of hardware accelerator for combinatorial computations and a strategy of such computations based on a reconfigurable hardware/software (RHS) model. The resulting hardware has been implemented on the basis of XCV812E Virtex FPGA, and it can be reused for different combinatorial problems. The complexity of the FPGA allows implementing whole systems that include the proposed accelerator linked to a host application-specific embedded controller for real time processing. The paper presents and analyzes a set of experiments with the proposed accelerator on the base of three well-known combinatorial problems that are a Boolean satisfiability (SAT), a traveling salesman problem (TSP) and a covering problem. The results have shown that the proposed architecture together with the respective methods and algorithms allow to reduce the time of computations significantly.
IFAC Proceedings Volumes, Jul 1, 2003
The Hardware C++ language (HC++) was developed to explore the object-oriented paradigm in the mul... more The Hardware C++ language (HC++) was developed to explore the object-oriented paradigm in the multilevel specification of digital systems. The main motivation for its development was the verification that present hardware description languages do not fully support the object oriented approach and the need for object-oriented technology in hardware description languages in order to face the increasing complexity hardware systems. (...) Keywords: HDL; OOP Ph. D., 1996 more info. http://opac.ua.pt/F/?func=find-b&find_code=SYS&REQUEST=000085962
This paper addresses the design of a Reprogrammable Combinatorial Processor (RCP) on the basis of... more This paper addresses the design of a Reprogrammable Combinatorial Processor (RCP) on the basis of reconfigurable circuits such as FPGA. The RCP is intended to be used for solving different combinatorial problems formulated over discrete matrices. From a structural point of view the RCP is a composition of a Reconfigurable Control Unit (RCU) and a Reconfigurable Function Unit (RFU). Each unit consists of hardwired (fixed) and programmable components. The paper considers and analyses methods, which can be used for logic synthesis and optimisation of RCP based on such decomposition. 1.INTRODUCTION Many practical applications invoke various combinatorial problems that have to be solved. There is a number of powerful algorithms and software tools that enable us to find their exact and approximate solutions on general-purpose computers. However the computational complexity of some combinatorial algorithms [1] makes it difficult (and sometimes even impossible) to find appropriate results i...
The present dissertation describes the project of a neural digital virtual processor to be fabric... more The present dissertation describes the project of a neural digital virtual processor to be fabricated in VLSI technology, and its development procedure, making use of a hardware description language - Verilog HDL. Through Verilog and its simulator Verilog-XL, the neural processor was designed and a simulation framework for the overall processing system - neurocomputer, was built. (...) Keywords: neural networks; parallel processing; verilog M.S., 1995 more info. http://opac.ua.pt/F/?func=find-b&find_code=SYS&REQUEST=000074177
Electronica E Telecomunicacoes, 2000
Finite state machines (FSM) have been a topic of great importance in the last five decades and ha... more Finite state machines (FSM) have been a topic of great importance in the last five decades and have been used ti specify and implement control units. Due to the increasing complexity of control units and since the FSM model does not explicitly support hierarchy and concurrency, new state-based models with hieararchical and concurrent constructions were proposed in order to overcome the limitations of conventional FSM model and allowing the specification of complex control units in a top-down manner. (...) Keywords: finite state machines; hierarchical specification of control units; logic synthesis; VHDL simulation Ph.D., 1999 more info. - http://opac.ua.pt/F/?func=find-b&find_code=SYS&REQUEST=000123591
2015 23rd International Conference on Software, Telecommunications and Computer Networks (SoftCOM), 2015
This paper presents the EaSys language, which can be used to model and design digital systems. It... more This paper presents the EaSys language, which can be used to model and design digital systems. It is an extension to the C++ object-oriented language, implemented through a class library, which adds to the base language a set of useful abstractions and mechanisms for hardware modelling. To write, compile and debug a system model written in EaSys, only standard C++ development tools are needed. This language is particularly useful to develop complex systems composed of hardware and software components because it promotes the use of a single language in the entire design flow.
Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216)
It is known that the majority of combinatorial tasks can be formulated on logic (Boolean, ternary... more It is known that the majority of combinatorial tasks can be formulated on logic (Boolean, ternary or some other) matrices, which further might be used to solve many problems of discrete optimization, such as finding the shortest and longest path in a graph, map coloring, set partitioning, etc. These problems appear in particular in embedded control systems that deal with technological processes (such as transfer line, assembly line, etc.), traffic management and other application areas. The paper presents a formal description of matrix combinatorial problems and suggests dynamically reconfigurable (FPGA-based) parallel computational devices that allow to solve them. Synthesis of these devices can be performed with the aid of software tools developed for PC computers in Visual C++.
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Papers by Antonio Ferrari