The book presents a comprehensive introduction to custom VLSI design in the complementary MOS (CM... more The book presents a comprehensive introduction to custom VLSI design in the complementary MOS (CMOS) technologies and contains a large number of practical design examples. Topics discussed include CMOS circuits, MOS transistor theory, CMOS processing technology, ...
Circuits, Interconnections, and Packaging for VLSI. HB Bakoglu 1990. Take advantage of this exper... more Circuits, Interconnections, and Packaging for VLSI. HB Bakoglu 1990. Take advantage of this expert treatment of high-speed VLSI circuits from a systems perspective. The volume offers a complete analysis of VLSI interconnections ...
… , 1999. Proceedings. 14th IEEE Symposium on, Jan 1, 1999
Binary carry-propagating addition can be efficiently expressed as a prefix computation. Several e... more Binary carry-propagating addition can be efficiently expressed as a prefix computation. Several examples of adders based on such a formulation have been published, and efficient implementations are numerous. Chief among the known constructions are those of Kogge & Stone and Ladner & Fischer. In this work we show that these are end cases of a large family of addition structures, all of which share the attractive property of minimum logical depth. The intermediate structures allow trade-offs between the amount of internal wiring and the fanout of intermediate nodes, and can thus usually achieve a more attractive combination of speed and area/power cost than either of the known end-cases. Rules for the construction of such adders are given, as are examples of realistic 32b designs implemented in an industrial 0u25 CMOS process.
This paper describes how a w-bit prefix-type carry-lookahead adder may be modified to yield more ... more This paper describes how a w-bit prefix-type carry-lookahead adder may be modified to yield more than one result per operation. The modified adder, called a 'flagged prefix adder', adds two 2's-complement numbers to give a sum S equals A + B but returns anyone of the ...
This paper presents a one-shot batch process that generates a wide range of designs for a group o... more This paper presents a one-shot batch process that generates a wide range of designs for a group of parallel prefix adders. The prefix adders are represented by two two-dimensional matrixes and two vectors. This matrix representation makes it possible to compose two functions for gate sizing which calculate the delay and the total transistor width of the carry propagation graph of adders. After gate sizing, the critical path net-lists of the carry propagation graph are generated from the matrix representation for spice delay calculation. The process is illustrated by generating sets of delay and total transistor width pairs for 32-bit and 64-bit cases.
Motivated by emerging battery-operated applications that demand intensive computation in portable... more Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining coniputational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architectural-based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption.
Page 1. 20 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 1, FEBR... more Page 1. 20 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 1, FEBRUARY 2002 Performance Analysis of Low-Power 1-Bit CMOS Full Adder Cells Ahmed M. Shams, Member ...
A novel low power and low transistor count static energy recovery full adder (SERF) is presented ... more A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this paper. The power consumption and general characteristics of the SERF adder are then compared against three low power full adders; the transmission function adder (TFA), the dual value logic (DVL) adder and the fourteen transistor (14T) full adder. The proposed SERF adder design was proven to be superior to the other three designs in power dissipation and area, and second in propagation delay only to the DVL adder. The combination of low power and low transistor count makes the new SERF cell a viable option for low power design.
Circuits and Systems II: Analog and …, Jan 1, 2002
... Index TermsArithmetic circuit, full adder, low power, very large-scale integration (VLSI), X... more ... Index TermsArithmetic circuit, full adder, low power, very large-scale integration (VLSI), XORXNOR. I. INTRODUCTION ... 780786, July 1994. [2] R. Shalem, E. John, and LK John, A novel low power energy recovery full adder cell, in Proc. IEEE Great Lakes VLSI Symp., Feb. ...
The 1-bit full adder circuit is a very important component in the design of application specific ... more The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64% faster.
… , 2001. ISCAS 2001. The 2001 IEEE …, Jan 1, 2001
Power consumption has recently become a major design issue due to the rapid growth in the technol... more Power consumption has recently become a major design issue due to the rapid growth in the technology of mobile communications and other portable applications using portable power supplies. The need for low power dissipation systems has motivated the development of ...
The book presents a comprehensive introduction to custom VLSI design in the complementary MOS (CM... more The book presents a comprehensive introduction to custom VLSI design in the complementary MOS (CMOS) technologies and contains a large number of practical design examples. Topics discussed include CMOS circuits, MOS transistor theory, CMOS processing technology, ...
Circuits, Interconnections, and Packaging for VLSI. HB Bakoglu 1990. Take advantage of this exper... more Circuits, Interconnections, and Packaging for VLSI. HB Bakoglu 1990. Take advantage of this expert treatment of high-speed VLSI circuits from a systems perspective. The volume offers a complete analysis of VLSI interconnections ...
… , 1999. Proceedings. 14th IEEE Symposium on, Jan 1, 1999
Binary carry-propagating addition can be efficiently expressed as a prefix computation. Several e... more Binary carry-propagating addition can be efficiently expressed as a prefix computation. Several examples of adders based on such a formulation have been published, and efficient implementations are numerous. Chief among the known constructions are those of Kogge & Stone and Ladner & Fischer. In this work we show that these are end cases of a large family of addition structures, all of which share the attractive property of minimum logical depth. The intermediate structures allow trade-offs between the amount of internal wiring and the fanout of intermediate nodes, and can thus usually achieve a more attractive combination of speed and area/power cost than either of the known end-cases. Rules for the construction of such adders are given, as are examples of realistic 32b designs implemented in an industrial 0u25 CMOS process.
This paper describes how a w-bit prefix-type carry-lookahead adder may be modified to yield more ... more This paper describes how a w-bit prefix-type carry-lookahead adder may be modified to yield more than one result per operation. The modified adder, called a 'flagged prefix adder', adds two 2's-complement numbers to give a sum S equals A + B but returns anyone of the ...
This paper presents a one-shot batch process that generates a wide range of designs for a group o... more This paper presents a one-shot batch process that generates a wide range of designs for a group of parallel prefix adders. The prefix adders are represented by two two-dimensional matrixes and two vectors. This matrix representation makes it possible to compose two functions for gate sizing which calculate the delay and the total transistor width of the carry propagation graph of adders. After gate sizing, the critical path net-lists of the carry propagation graph are generated from the matrix representation for spice delay calculation. The process is illustrated by generating sets of delay and total transistor width pairs for 32-bit and 64-bit cases.
Motivated by emerging battery-operated applications that demand intensive computation in portable... more Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining coniputational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architectural-based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption.
Page 1. 20 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 1, FEBR... more Page 1. 20 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 1, FEBRUARY 2002 Performance Analysis of Low-Power 1-Bit CMOS Full Adder Cells Ahmed M. Shams, Member ...
A novel low power and low transistor count static energy recovery full adder (SERF) is presented ... more A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this paper. The power consumption and general characteristics of the SERF adder are then compared against three low power full adders; the transmission function adder (TFA), the dual value logic (DVL) adder and the fourteen transistor (14T) full adder. The proposed SERF adder design was proven to be superior to the other three designs in power dissipation and area, and second in propagation delay only to the DVL adder. The combination of low power and low transistor count makes the new SERF cell a viable option for low power design.
Circuits and Systems II: Analog and …, Jan 1, 2002
... Index TermsArithmetic circuit, full adder, low power, very large-scale integration (VLSI), X... more ... Index TermsArithmetic circuit, full adder, low power, very large-scale integration (VLSI), XORXNOR. I. INTRODUCTION ... 780786, July 1994. [2] R. Shalem, E. John, and LK John, A novel low power energy recovery full adder cell, in Proc. IEEE Great Lakes VLSI Symp., Feb. ...
The 1-bit full adder circuit is a very important component in the design of application specific ... more The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64% faster.
… , 2001. ISCAS 2001. The 2001 IEEE …, Jan 1, 2001
Power consumption has recently become a major design issue due to the rapid growth in the technol... more Power consumption has recently become a major design issue due to the rapid growth in the technology of mobile communications and other portable applications using portable power supplies. The need for low power dissipation systems has motivated the development of ...
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