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Pascal Masson
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2020 – today
- 2024
- [c12]Lucas Antunes Tambara, Paul Devoge, Pascal Masson, Julien Amouroux, Julien Dura, C. Rivero, Franck Julien:
MOSFET electron mobility enhancement using source/drain recess. DTTIS 2024: 1-4 - 2023
- [c11]Lucas Antunes Tambara
, Pascal Masson, Julien Amouroux, Stéphane Monfray, Julien Dura, Frederic Gianesello, Julien Babic, Romain Debroucke, Loic Welter, Siddhartha Dhar, Bernadette Gros, Clement Charbuillet, Franck Julien, Guillaume Bertrand, Arnaud Régnier, Alain Fleury:
Notched gate MOSFET for capacitance reduction in RF SOI technology. DTTIS 2023: 1-4 - [c10]Radouane Habhab
, Vincenzo Della Marca, Pascal Masson, Nadia Miridi, Clement Pribat, Simon Jeannot, Thibault Kempf, Marc Mantelli, Philippe Lorenzini, Jean-Marc Voisin, Arnaud Régnier, Stephan Niel, Francesco La Rosa:
40nm SONOS Embedded Select in Trench Memory. ESSDERC 2023: 21-24 - 2022
- [c9]Paul Devoge, Hassen Aziza, Philippe Lorenzini, Pascal Masson, Alexandre Malherbe, Franck Julien, Abderrezak Marzaki, Arnaud Régnier, Stephan Niel:
A Schmitt trigger to benchmark the performance of a new zero-cost transistor. ICECS 2022 2022: 1-4
2010 – 2019
- 2018
- [c8]Thibault Kempf, Vincenzo Della Marca, L. Baron, F. Maugain, Francesco La Rosa, Stephan Niel, Arnaud Régnier, Jean-Michel Portal, Pascal Masson:
Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip. IRPS 2018: 6 - 2015
- [c7]Jordan Innocenti, Franck Julien, Jean-Michel Portal, Laurent Lopez, Q. Hubert, Pascal Masson, Jacques Sonzogni, Stephan Niel, Arnaud Régnier:
Layout optimizations to decrease internal power and area in digital CMOS standard cells. MIPRO 2015: 1582-1587 - [c6]Jordan Innocenti, Loïc Welter, Nicolas Borrel, Franck Julien, Jean-Michel Portal, Jacques Sonzogni, Laurent Lopez, Pascal Masson, Stephan Niel, Philippe Dreux, Julia Castellan:
Dynamic current reduction of CMOS digital circuits through design and process optimization. PATMOS 2015: 77-81 - 2014
- [c5]Benjamin Rebuffat, Pascal Masson, Jean-Luc Ogier, Marc Mantelli, Romain Laffont:
Effect of AC stress on oxide TDDB and trapped charge in interface states. ISIC 2014: 416-419 - [c4]Jordan Innocenti, Loic Welter, Franck Julien, Laurent Lopez, Jacques Sonzogni, Stephan Niel, Arnaud Régnier, Emmanuel Paire, Karen Labory, Eric Denis, Jean-Michel Portal, Pascal Masson:
Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology. MWSCAS 2014: 897-900 - 2013
- [c3]Benjamin Rebuffat, Vincenzo Della Marca, Pascal Masson, Jean-Luc Ogier, Marc Mantelli, Olivier Paulet, Laurent Lopez, Romain Laffont:
Effect of ions presence in the SiOCH inter metal dielectric structure. ESSDERC 2013: 218-221 - 2012
- [j4]Guillaume Just, Vincenzo Della Marca, Arnaud Régnier, Jean-Luc Ogier, Jérémy Postel-Pellerin, Jean-Michel Portal, Pascal Masson:
Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability. J. Low Power Electron. 8(5): 717-724 (2012) - [j3]R. Llido, Pascal Masson, Arnaud Régnier, Vincent Goubier, Gérald Haller, Vincent Pouget, Dean Lewis:
Effects of 1064 nm laser on MOS capacitor. Microelectron. Reliab. 52(9-10): 1816-1821 (2012) - [j2]Philippe Chiquet, Pascal Masson, Romain Laffont, Gilles Micolau, Jérémy Postel-Pellerin, Frédéric Lalande, Bernard Bouteille, Jean-Luc Ogier:
Investigation of the effects of constant voltage stress on thin SiO2 layers using dynamic measurement protocols. Microelectron. Reliab. 52(9-10): 1895-1900 (2012)
2000 – 2009
- 2006
- [c2]B. Saillet, Arnaud Régnier, Jean-Michel Portal, B. Delsuc, Romain Laffont, Pascal Masson, Rachid Bouchakour:
MM11 based flash memory cell model including characterization procedure. ISCAS 2006 - 2005
- [j1]Fabien Gilibert, Denis Rideau, Alexandre Dray, Francois Agut, Michel Minondo, Andre Juge, Pascal Masson, Rachid Bouchakour:
Characterization and Modeling of Gate-Induced-Drain-Leakage. IEICE Trans. Electron. 88-C(5): 829-837 (2005) - 2004
- [c1]Sandrine Bernardini
, Jean-Michel Portal, Pascal Masson:
A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology. DATE 2004: 1404-1405
Coauthor Index
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