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ORCIDICCAD 2018: San Diego, CA, USA
- Iris Bahar:
Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018. ACM 2018, ISBN 978-1-4503-5950-4 - Jai-Ming Lin, Tai-Ting Chen, Yen-Fu Chang, Wei-Yi Chang, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu:
A fast thermal-aware fixed-outline floorplanning methodology based on analytical models. 1:1-1:8 - Wenxing Zhu, Zhipeng Huang, Jianli Chen, Yao-Wen Chang:
Analytical solution of Poisson's equation and its application to VLSI global placement. 2 - Jianli Chen, Li Yang
, Zheng Peng, Wenxing Zhu, Yao-Wen Chang:
Novel proximal group ADMM for placement considering fogging and proximity effects. 3 - Shih-Chun Chen, Richard Sun, Yao-Wen Chang:
Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems. 4 - Samah Mohamed Saeed, Xiaotong Cui, Alwin Zulehner, Robert Wille, Rolf Drechsler, Kaijie Wu, Ramesh Karri:
IC/IP piracy assessment of reversible logic. 5 - Abhishek Chakraborty, Yuntao Liu, Ankur Srivastava:
TimingSAT: timing profile embedded SAT attack. 6 - Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran:
Towards provably-secure analog and mixed-signal locking against overproduction. 7 - Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel:
Best of both worlds: integration of split manufacturing and camouflaging into a security-driven CAD flow for 3D ICs. 8 - Sebastian Vogel, Mengyu Liang, Andre Guntoro, Walter Stechele, Gerd Ascheid:
Efficient hardware acceleration of CNNs using logarithmic data representation with arbitrary log-base. 9 - Jaehyeong Sim, Hoseok Seol, Lee-Sup Kim:
NID: processing binary convolutional neural network in commodity DRAM. 10 - Zhenghao Peng, Xuyang Chen, Chengwen Xu, Naifeng Jing, Xiaoyao Liang, Cewu Lu, Li Jiang:
AXNet: approximate computing using an end-to-end trainable neural network. 11:1-11:8 - Valentino Peluso, Andrea Calimera:
Scalable-effort ConvNets for multilevel classification. 12 - Shubham Rai, Srivatsa Rangachar Srinivasa, Patsy Cadareanu, Xunzhao Yin, Xiaobo Sharon Hu, Pierre-Emmanuel Gaillardon, Vijaykrishnan Narayanan, Akash Kumar:
Emerging reconfigurable nanotechnologies: can they support future electronics? 13 - Giyoung Yang, Taewhan Kim:
Design and algorithm for clock gating and flip-flop co-optimization. 14 - Jai-Ming Lin, Jhih-Sheng Syu, I-Ru Chen:
Macro-aware row-style power delivery network design for better routability. 15 - Baixin Chen, Umamaheswara Rao Tida, Cheng Zhuo, Yiyu Shi:
Modeling and optimization of magnetic core TSV-inductor for on-chip DC-DC converter. 16 - Yen-Chun Fang, Heng-Yi Lin, Min-Yan Su, Chien-Mo James Li, Eric Jia-Wei Fang:
Machine-learning-based dynamic IR drop prediction for ECO. 17 - M. Sadegh Riazi, Farinaz Koushanfar:
Privacy-preserving deep learning and inference. 18 - Rosario Cammarota, Indranil Banerjee, Ofer Rosenberg:
Machine learning IP protection. 19 - Bita Darvish Rouhani, Mohammad Samragh, Mojan Javaheripi, Tara Javidi, Farinaz Koushanfar:
Assured deep learning: practical defense against adversarial attacks. 20 - Hang Lu, Xin Wei, Ning Lin, Guihai Yan, Xiaowei Li:
Tetris: re-architecting convolutional neural network computation for machine learning accelerators. 21 - Dawen Xu, Kaijie Tu, Ying Wang, Cheng Liu, Bingsheng He, Huawei Li:
FCN-engine: accelerating deconvolutional layers in classic CNN processors. 22 - Dimitrios Stamoulis, Ting-Wu (Rudy) Chin, Anand Krishnan Prakash, Haocheng Fang, Sribhuvan Sajja, Mitchell Bognar, Diana Marculescu:
Designing adaptive neural networks for energy-constrained image classification. 23 - Jeff Jun Zhang, Siddharth Garg:
FATE: fast and accurate timing error prediction framework for low power DNN accelerator design. 24 - Debayan Roy, Michael Balszun, Thomas Heurung, Samarjit Chakraborty, Amol Naik:
Waterfall is too slow, let's go Agile: multi-domain coupling for synthesizing automotive cyber-physical systems. 25 - Tianshu Wei, Xiaoming Chen, Xin Li, Qi Zhu:
Model-based and data-driven approaches for building automation and control. 26 - Swaminathan Narayanaswamy, Sangyoung Park, Sebastian Steinhorst, Samarjit Chakraborty:
Design automation for battery systems. 27 - Kevin Laeufer, Jack Koenig, Donggyu Kim, Jonathan Bachrach, Koushik Sen:
RFUZZ: coverage-directed fuzz testing of RTL on FPGAs. 28 - Gabriel A. G. Andrade, Marleson Graf, Nícolas Pfeifer, Luiz C. V. dos Santos:
Steep coverage-ascent directed test generation for shared-memory verification of multicore chips. 29 - Rafael Dutra, Jonathan Bachrach, Koushik Sen:
SMTSampler: efficient stimulus generation from complex SMT constraints. 30 - Meng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang:
DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning. 31 - Yun Long, Taesik Na, Prakshi Rastogi, Karthik Rao, Asif Islam Khan, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
A ferroelectric FET based power-efficient architecture for data-intensive computing. 32 - Fan Chen, Hai Li:
EMAT: an efficient multi-task architecture for transfer learning using ReRAM. 33 - Haoran Li, Zhongyuan Tian, Rafael K. V. Maeda, Xuanqi Chen, Jun Feng, Jiang Xu:
Co-manage power delivery and consumption for manycore systems using reinforcement learning. 34 - Wentai Zhang, Hanxian Huang, Jiaxi Zhang, Ming Jiang, Guojie Luo:
Adaptive-precision framework for SGD using deep Q-learning. 35 - Chih-Hsuan Yen, Wei-Ming Chen, Pi-Cheng Hsiu, Tei-Wei Kuo:
Differentiated handling of physical scenes and virtual objects for mobile augmented reality. 36 - Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, Gi-Joon Nam:
DATC RDF: an academic flow from logic synthesis to detailed routing. 37 - Xin Fan, Rui Wang, Tobias Gemmeke:
Physical modeling of bitcell stability in subthreshold SRAMs for leakage-area optimization under PVT variations. 38 - Yutaka Masuda, Jun Nagayama, Hirotaka Takeno, Yoshimasa Ogawa, Yoichi Momiyama, Masanori Hashimoto:
Comparing voltage adaptation performance between replica and in-situ timing monitors. 39 - Tengtao Li, Sachin S. Sapatnekar:
Strain-aware performance evaluation and correction for OTFT-based flexible displays. 40 - Ping-Hsien Lin, Yu-Ming Chang, Yung-Chun Li, Wei-Chen Wang, Chien-Chung Ho, Yuan-Hao Chang:
Achieving fast sanitization with zero live data copy for MLC flash memory. 41 - Hoda Aghaei Khouzani, Chen Liu, Chengmo Yang:
Architecting data placement in SSDs for efficient secure deletion implementation. 42 - Jacob R. Stevens, Ashish Ranjan, Anand Raghunathan:
AxBA: an approximate bus architecture framework. 43 - Francesco Regazzoni, Cesare Alippi, Ilia Polian:
Security: the dark side of approximate computing? 44 - Johanna Sepúlveda, Cezar Reinbrecht, Jean-Philippe Diguet:
Security aspects of neuromorphic MPSoCs. 45 - Todd M. Austin, Valeria Bertacco, Baris Kasikci, Sharad Malik, Mohit Tiwari:
Vulnerability-tolerant secure architectures. 46 - Joseph L. Greathouse, Gabriel H. Loh:
Machine learning for performance and power modeling of heterogeneous systems. 47 - Ryan Gary Kim, Janardhan Rao Doppa, Partha Pratim Pande:
Machine learning for design space exploration and optimization of manycore systems. 48 - Shi Jin, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu:
Failure prediction based on anomaly detection for complex core routers. 49 - Haiyue Song, Chengwen Xu, Qiang Xu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang, Li Jiang:
Invocation-driven neural approximate computing with a multiclass-classifier and multiple approximators. 50 - M. Hassan Najafi, David J. Lilja, Marc D. Riedel:
Deterministic methods for stochastic computing using low-discrepancy sequences. 51 - Jorge Echavarria, Stefan Wildermann, Jürgen Teich:
Design space exploration of multi-output logic function approximations. 52 - Qian Lou, Wujie Wen, Lei Jiang:
3DICT: a reliable and QoS capable mobile process-in-memory architecture for lookup-based CNNs in 3D XPoint ReRAMs. 53 - Bing Wu, Dan Feng, Wei Tong, Jingning Liu, Shuai Li, Mingshun Yang, Chengning Wang, Yang Zhang:
Aliens: a novel hybrid architecture for resistive random-access memory. 54 - Saransh Gupta, Mohsen Imani, Tajana Rosing:
FELIX: fast and energy-efficient logic in memory. 55 - Xiaofan Zhang, Junsong Wang, Chao Zhu, Yonghua Lin, Jinjun Xiong, Wen-Mei W. Hwu, Deming Chen:
DNNBuilder: an automated tool for building high-performance DNN hardware accelerators for FPGAs. 56 - Yufei Ma, Tu Zheng, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs. 57 - Xuechao Wei, Yun Liang, Xiuhong Li, Cody Hao Yu, Peng Zhang, Jason Cong:
TGPA: tile-grained pipeline architecture for low latency CNN inference. 58 - Abhrajit Sengupta, Mohammed Thari Nabeel, Mohammed Ashraf, Ozgur Sinanoglu:
Customized locking of IP blocks on a multi-million-gate SoC. 59 - Jörg Henkel, Jürgen Teich, Stefan Wildermann, Hussam Amrouch:
Dynamic resource management for heterogeneous many-cores. 60 - Ganapati Bhat, Sumit K. Mandal, Ujjwal Gupta, Ümit Y. Ogras:
Online learning for adaptive optimization of heterogeneous SoCs. 61 - Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Diana Marculescu, Radu Marculescu:
Hybrid on-chip communication architectures for heterogeneous manycore systems. 62 - Yu-Hsiang Cheng, Ding-Wei Huang, Wai-Kei Mak, Ting-Chi Wang:
A practical detailed placement algorithm under multi-cell spacing constraints. 63 - Yu-Wei Tseng, Yao-Wen Chang:
Mixed-cell-height placement considering drain-to-drain abutment. 64 - Ziran Zhu, Xingquan Li, Yuhang Chen, Jianli Chen, Wenxing Zhu, Yao-Wen Chang:
Mixed-cell-height legalization considering technology and region constraints. 65 - Jianli Chen, Peng Yang, Xingquan Li, Wenxing Zhu, Yao-Wen Chang:
Mixed-cell-height placement with complex minimum-implant-area constraints. 66 - Poovaiah M. Palangappa, Kartik Mohanram:
RAPID: read acceleration for improved performance and endurance in MLC/TLC NVMs. 67 - Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto:
Sneak path free reconfiguration of via-switch crossbars based FPGA. 68 - Zhenhua Zhu, Jilan Lin, Ming Cheng, Lixue Xia, Hanbo Sun, Xiaoming Chen, Yu Wang, Huazhong Yang:
Mixed size crossbar based RRAM CNN accelerator with overlapped mapping method. 69 - Hidenori Gyoten, Masayuki Hiromoto, Takashi Sato:
Enhancing the solution quality of hardware ising-model solver via parallel tempering. 70 - Siyue Wang, Xiao Wang, Pu Zhao, Wujie Wen, David R. Kaeli, Peter Chin, Xue Lin:
Defensive dropout for hardening deep neural networks under adversarial attacks. 71:1-71:8 - Ganapati Bhat, Ranadeep Deb, Vatika Vardhan Chaurasia, Holly Shill, Ümit Y. Ogras:
Online human activity recognition using low-power wearable devices. 72 - Mohammed Shayan, Sukanta Bhattacharjee, Tung-Che Liang, Jack Tang, Krishnendu Chakrabarty, Ramesh Karri:
Shadow attacks on MEDA biochips. 73 - Emanuel Regnath, Sebastian Steinhorst:
LeapChain: efficient blockchain verification for embedded IoT. 74 - Yanqi Liu, Alessandro Costantini, R. Iris Bahar, Zhiqiang Sui, Zhefan Ye, Shiyang Lu, Odest Chadwicke Jenkins:
Robust object estimation using generative-discriminative inference for secure robotics applications. 75 - Sai Manoj P. D., Sairaj Amberkar, Setareh Rafatirad, Houman Homayoun:
Efficient utilization of adversarial training towards robust machine learners and its analysis. 78 - Luca G. Amarù, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni De Micheli, Mathias Soeken:
Majority logic synthesis. 79 - Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Nvidia Corporation:
RouteNet: routability prediction for mixed-size designs using convolutional neural network. 80 - Andrew B. Kahng, Lutong Wang, Bangqi Xu:
TritonRoute: an initial detailed router for advanced VLSI technologies. 81 - Fan-Keng Sun, Hao Chen, Ching-Yu Chen, Chen-Hao Hsu, Yao-Wen Chang:
A multithreaded initial detailed routing algorithm considering global routing guides. 82 - Bing-Hui Jiang, Hung-Ming Chen:
Extending ML-OARSMT to net open locator with efficient and effective boolean operations. 83 - Chia-Chih Chi, Jie-Hong R. Jiang:
Logic synthesis of binarized neural networks for efficient circuit implementation. 84 - Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang:
Canonicalization of threshold logic representation and its applications. 85 - Zhuangzhuang Zhou, Yue Yao, Shuyang Huang, Sanbao Su, Chang Meng, Weikang Qian:
DALS: delay-driven approximate logic synthesis. 86 - Vinicius N. Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato P. Ribas, André Inácio Reis:
Unlocking fine-grain parallelism for AIG rewriting. 87 - Zhenghong Jiang, Steve Dai, G. Edward Suh, Zhiru Zhang:
High-level synthesis with timing-sensitive information flow enforcement. 88 - Wei Hu, Armaiti Ardeshiricham, Mustafa S. Gobulukoglu, Xinmu Wang, Ryan Kastner:
Property specific information flow analysis for hardware security verification. 89 - Mengmei Ye, Xianglong Feng, Sheng Wei:
HISA: hardware isolation-based secure architecture for CPU-FPGA embedded systems. 90 - Timothy Linscott, Pete Ehrett, Valeria Bertacco, Todd M. Austin:
SWAN: mitigating hardware trojans with design ambiguity. 91 - Raj Gautam Dutta, Feng Yu, Teng Zhang, Yaodan Hu, Yier Jin:
Security for safety: a path toward building trusted autonomous vehicles. 92 - Martin Geier, Fabian Franzen, Samarjit Chakraborty:
Hardware-accelerated data acquisition and authentication for high-speed video streams on future heterogeneous automotive processing platforms. 93 - Hengyi Liang, Matthew Jagielski, Bowen Zheng, Chung-Wei Lin, Eunsuk Kang, Shinichi Shiraishi, Cristina Nita-Rotaru, Qi Zhu:
Network and system level security in connected vehicle applications. 94 - Qian Chen, Azizeh Khaled Sowan, Shouhuai Xu:
A safety and security architecture for reducing accidents in intelligent transportation systems. 95 - Steve Bigalke, Jens Lienig, Göran Jerke, Jürgen Scheible, Roland Jancke:
The need and opportunities of electromigration-aware integrated circuit design. 96 - Chunfeng Cui, Zheng Zhang:
Uncertainty quantification of electronic and photonic ICs with non-Gaussian correlated process variations. 97 - Hanbin Hu, Peng Li, Jianhua Z. Huang:
Parallelizable Bayesian optimization for analog and mixed-signal rare failure detection with high coverage. 98 - Pengwen Chen, Chung-Kuan Cheng, Dongwon Park, Xinyuan Wang:
Transient circuit simulation for differential algebraic systems using matrix exponential. 99 - Mengchu Li, Tsun-Ming Tseng, Davide Bertozzi, Mahdi Tala, Ulf Schlichtmann:
CustomTopo: a topology generation method for application-specific wavelength-routed optical NoCs. 100 - Ayse K. Coskun, Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Vaishnav Srinivas:
A cross-layer methodology for design and optimization of networks in 2.5D systems. 101 - Yong Hu, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Wavefront-MCTS: multi-objective design space exploration of NoC architectures based on Monte Carlo tree search. 102 - Young-kyu Choi, Jason Cong:
HLS-based optimization and design space exploration for applications with variable loop bounds. 103 - Kenneth O'Neal, Mitch Liu, Hans Tang, Amin Kalantar, Kennen DeRenard, Philip Brisk:
HLSPredict: cross platform performance prediction for FPGA high-level synthesis. 104 - Duseok Kang, Euiseok Kim, Inpyo Bae, Bernhard Egger, Soonhoi Ha:
C-GOOD: C-code generation framework for optimized on-device deep learning. 105 - Ghada Dessouky, Tigist Abera, Ahmad Ibrahim, Ahmad-Reza Sadeghi:
LiteHAX: lightweight hardware-assisted attestation of program execution. 106 - Majid Sabbagh, Yunsi Fei, Thomas Wahl, A. Adam Ding:
SCADET: a side-channel attack detection tool for tracking prime+probe. 107 - Leonidas Kosmidis, Cristian Maxim, Victor Jégu, Francis Vatrinet, Francisco J. Cazorla:
Industrial experiences with resource management under software randomization in ARINC653 avionics environments. 108 - Coenrad J. Fourie:
Single flux quantum circuit technology and CAD overview. 109 - Massoud Pedram, Yanzhi Wang:
Design automation methodology and tools for superconductive electronics. 110:1-110:6 - Pei-Yi Cheng, Kazuyoshi Takagi, Tsung-Yi Ho:
Multi-terminal routing with length-matching for rapid single flux quantum circuits. 111 - Chenguang Wang, Yici Cai, Haoyi Wang, Qiang Zhou:
Electromagnetic equalizer: an active countermeasure against EM side-channel attack. 112 - Chao Luo, Yunsi Fei, David R. Kaeli:
GPU acceleration of RSA is vulnerable to side-channel timing attacks. 113 - Falk Schellenberg, Dennis R. E. Gnad, Amir Moradi, Mehdi Baradaran Tahoori:
Remote inter-chip power analysis side-channel attacks at board-level. 114 - Chao Luo, Yunsi Fei, David R. Kaeli:
Effective simple-power analysis attacks of elliptic curve cryptography on embedded systems. 115 - Yuze Chi, Jason Cong, Peng Wei, Peipei Zhou:
SODA: stencil with optimized dataflow architecture. 116 - Jason Cong, Jie Wang:
PolySA: polyhedral-based systolic array auto-compilation. 117 - Wensong Li, Fan Yang, Hengliang Zhu, Xuan Zeng, Dian Zhou:
An efficient data reuse strategy for multi-pattern data access. 118 - Hou-Jen Ko, Zhiyuan Li, Samuel P. Midkiff:
Optimizing data layout and system configuration on FPGA-based heterogeneous platforms. 119 - Kofi Otseidu, Tianyu Jia, Joshua Bryne, Levi J. Hargrove, Jie Gu:
Design and optimization of edge computing distributed neural processor for biomedical rehabilitation with sensor fusion. 120 - Bon Woong Ku, Yu Liu, Yingyezhe Jin, Peng Li, Sung Kyu Lim:
Area-efficient and low-power face-to-face-bonded 3D liquid state machine design. 121 - Shaahin Angizi, Zhezhi He, Deliang Fan:
DIMA: a depthwise CNN in-memory accelerator. 122 - Ying Zhu, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann:
Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips. 123 - Hengyang Zhao, Sheldon X.-D. Tan:
Multi-physics-based FEM analysis for post-voiding analysis of electromigration failure effects. 124 - Hussam Amrouch, Victor M. van Santen, Jörg Henkel:
Estimating and optimizing BTI aging effects: from physics to CAD. 125 - A. K. M. Mahfuzul Islam, Hidetoshi Onodera:
PVT2: process, voltage, temperature and time-dependent variability in scaled CMOS process. 126 - Daniel Mueller-Gritschneder, Uzair Sharif, Ulf Schlichtmann:
Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-ML. 127 - Robert Wille, Austin G. Fowler, Yehuda Naveh:
Computer-aided design for quantum computation. 128 - Alireza Mahzoon, Daniel Große, Rolf Drechsler:
PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers. 129 - Yue Xing, Bo-Yuan Huang, Aarti Gupta, Sharad Malik:
A formal instruction-level GPU model for scalable verification. 130 - Steven Herbst, ByongChan Lim, Mark Horowitz:
Fast FPGA emulation of analog dynamics in digitally-driven systems. 131 - Kent W. Nixon, Jiachen Mao, Juncheng Shen, Huanrui Yang, Hai (Helen) Li, Yiran Chen:
SPN dash: fast detection of adversarial attacks on mobile via sensor pattern noise fingerprinting. 132 - Jia Guo, Miodrag Potkonjak:
Watermarking deep neural networks for embedded systems. 133 - Bita Darvish Rouhani, Mohammad Samragh, Mojan Javaheripi, Tara Javidi, Farinaz Koushanfar:
DeepFense: online accelerated defense against adversarial deep learning. 134 - Liangzhen Lai, Naveen Suda:
Enabling deep learning at the IoT edge. 135 - An-Chieh Cheng, Jin-Dong Dong, Chi-Hung Hsu, Shu-Huan Chang, Min Sun, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan:
Searching toward pareto-optimal device-aware neural architectures. 136 - Diana Marculescu, Dimitrios Stamoulis, Ermao Cai:
Hardware-aware machine learning: modeling and optimization. 137
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